MIPI D-PHY Property Reference

All of these MIPI D-PHY block properties are applicable to the Titanium and Topaz families.

Table 1. MIPI D-PHY General Properties (All Modes)x is RX or TX.
API Name GUI Name Values
DATA_WIDTH Width of the data bus 8, 16
ENABLE_TURNAROUND Enable Turn-around Feature in Data Lane 0 0, 1
NAME Instance Name Instance Name
NUM_DATA_LANES Number of data lanes 1, 2, 4
PHY_LANE_0 Physical Lane 0 Map to Logical Lane clk, data0, data1, data2, data3, unused
PHY_LANE_1 Physical Lane 1 Map to Logical Lane clk, data0, data1, data2, data3, unused
PHY_LANE_2 Physical Lane 2 Map to Logical Lane clk, data0, data1, data2, data3, unused
PHY_LANE_3 Physical Lane 3 Map to Logical Lane clk, data0, data1, data2, data3, unused
PHY_LANE_4 Physical Lane 4 Map to Logical Lane clk, data0, data1, data2, data3, unused
PHY_LANE_0_PN_SWAP Swap physical lane P/N on physical lane 0 0, 1
PHY_LANE_1_PN_SWAP Swap physical lane P/N on physical lane 1 0, 1
PHY_LANE_2_PN_SWAP Swap physical lane P/N on physical lane 2 0, 1
PHY_LANE_3_PN_SWAP Swap physical lane P/N on physical lane 3 0, 1
PHY_LANE_4_PN_SWAP Swap physical lane P/N on physical lane 4 0, 1
RESOURCE MIPI Resource MIPIx0, MIPIx1,MIPIx2, MIPIx3,
Table 2. MIPI D-PHY RX (Control, Status and Clock) Properties
API Name GUI Name Values
BUF_WORD_CLKOUT_HS_NAME Global Pin Name1 Pin name
CFG_CLK_FREQ Configuration Clock Frequency (MHz) 80 to 120
CFG_CLK_PIN Configuration Clock Pin Name Pin name
CFG_CLK_INVERT_EN Invert Configuration Clock 0, 1
DATA_RATE Data rate in Mbps 80 to 2500
LP_CLK_PIN LP Clock State Pin Name Pin name
RESET_N_PIN Active Low Reset Pin Name Pin name
RST0_N_PIN Active Low Async FIFO Reset0 Pin Name Pin name
RX_CLK_ACTIVE_HS_PIN Receiver Clock Active Pin Name Pin name
RX_ULPS_CLK_NOT_PIN Active Low ULP State Clock Lane Pin Name Pin name
RX_ULPS_ACTIVE_CLK_NOT_PIN Active Low ULP State Active Pin Name Pin name
STOPSTATE_CLK_PIN Stop State Clock Lane Pin Name Pin name
TX_CLK_ESC_PIN Escape Mode Transmit Clock Pin Name Pin name
TX_CLK_ESC_INVERT_EN Invert Escape Mode Transmit Clock 0, 1
WORD_CLKOUT_HS_CONN_TYPE HS Receive Byte/Word Clock Pin Connection Type gclk, rclk
WORD_CLKOUT_HS_PIN HS Receive Byte/Word Clock Pin Name Pin name
Table 3. MIPI D-PHY RX (Data Lanes) Propertiesn is 0, 1, 2, or 3
API Name GUI Name Values
BUF_RX_CLK_ESC_NAME Global Pin Name1 Pin name
DIRECTION_PIN Transmit/Receive Direction Pin Name Pin name
ERR_ESC_LANn_PIN Escape Entry Error Pin Name Pin name
ERR_CONTROL_LANn_PIN Control Error Pin Name Pin name
ERR_SOT_SYNC_HS_LANn_PIN State-of-Transmission (SOT) Sync Error Pin Name Pin name
ERR_SOT_HS_LANn_PIN State-of-Transmission (SOT) Error Pin Name Pin name
ERR_SYNC_ESC_PIN LP Data Transmit Synchronization Error Pin Name Pin name
ERR_CONTENTION_LP0_PIN LP0 Contention Error Pin Name Pin name
ERR_CONTENTION_LP1_PIN LP1 Contention Error Pin Name Pin name
FORCE_RX_MODE_PIN Force Receive Mode/Wait For Stop Pin Name Pin name
RX_CLK_ESC_CONN_TYPE Escape Mode Receive Clock Pin Connection Type normal, rclk
RX_CLK_ESC_LANn_PIN Escape Mode Receive Clock Pin Name Pin name
RX_ULPS_ESC_LANn_PIN Escape Mode ULP Pin Name Pin name
RX_ULPS_ACTIVE_NOT_LANn_PIN Active Low ULP State Data Lane Pin Name Pin name
RX_ACTIVE_HS_LANn_PIN HS Reception Active Pin Name Pin name
RX_VALID_HS_LANn_PIN HS Data Receive Valid Pin Name Pin name
RX_SYNC_HS_LANn_PIN HS Receiver Sync Observed Pin Name Pin name
RX_SKEW_CAL_HS_LANn_PIN HS Receiver Skew Calibration Pin Name Pin name
RX_DATA_HS_LANn_PIN HS Receive Data Bus Name Pin name
RX_LPDT_ESC_PIN Escape Mode LP Data Pin Name Pin name
RX_VALID_ESC_PIN Escape Mode Data Valid Pin Name Pin name
RX_DATA_ESC_PIN Escape Mode Data 7:0 Bus Name Pin name
RX_TRIGGER_ESC_PIN Escape Mode Receive Trigger 3:0 Bus Name Pin name
STOPSTATE_LANn_PIN Data Lane In Stop State Pin Name Pin name
TURN_REQUEST_PIN Turnaround Request Pin Name Pin name
TX_REQUEST_ESC_PIN Escape Mode Transmit Request Pin Name Pin name
TX_LPDT_ESC_PIN Escape LP Data Transmit Mode Pin Name Pin name
TX_VALID_ESC_PIN Escape Mode Transmit Data Valid Pin Name Pin name
TX_READY_ESC_PIN Escape Mode Transmit Ready Pin Name Pin name
TX_ULPS_ESC_PIN Escape ULP Transmit Mode Pin Name Pin name
TX_ULPS_EXIT_PIN Transmit ULP Exit Sequence Pin Name Pin name
TX_TRIGGER_ESC_PIN Escape Mode Transmit Trigger 3:0 Bus Name Pin name
TX_DATA_ESC_PIN Escape Mode Transmit Data 7:0 Bus Name Pin name
Table 4. MIPI D-PHY TX (Control, Status and Clock) Properties
API Name GUI Name Values
BUF_RX_CLK_ESC_NAME Global Pin Name1 Pin name
BUF_WORD_CLKOUT_HS_NAME Global Pin Name1 Pin name
ENABLE_SSC Enable Spread Spectrum Clock (SSC) 0, 1
PHY_BANDWIDTH Phy Bandwidth in Mbps 80 to 2500, Multiple of 10
PLL_SSC_AMP SSC Amplitude for MIPI Internal PLL (PPM) 2500 - 4999
PLL_SSC_AMP_INIT SSC Initial Amplitude for MIPI Internal PLL (PPM) 2501 - 5000
PLL_SSC_PERIOD SSC Frequency for MIPI Internal PLL (KHz) 30 - 33
PLL_SSC_EN_PIN PLL SSC Enable Pin Name Pin name
PLL_UNLOCK_PIN PLL Unlock State Pin Name Pin name
REF_CLK_FREQUENCY Reference Clock Frequency 12.0, 19.2, 25.0, 26.0, 27.0, 38.4, 52.0
REF_CLK_SELECT Reference Clock Source Type gpio , pll , core
RESET_N_PIN Active Low Reset Pin Name Pin name
RX_CLK_ESC_CONN_TYPE Escape Mode Receive Clock Connection Type normal, rclk
RX_CLK_ESC_PIN Escape Mode Receive Clock Pin Name Pin name
STOPSTATE_CLK_PIN Stop State Clock Lane Pin Name Pin name
TX_CLK_ESC_PIN Escape Mode Transmit Clock Pin Name Pin name
TX_CLK_ESC_INVERT_EN Invert Escape Mode Transmit Clock 0, 1
TX_REQUEST_HS_PIN HS Clock Request Pin Name Pin name
TX_ULPS_CLK_PIN ULP State Clock Lane Pin Name Pin name
TX_ULPS_EXIT_PIN ULP Exit Pin Name Pin name
TX_ULPS_ACTIVE_CLK_NOT_PIN Active Low ULP State Active Pin Name Pin name
WORD_CLKOUT_HS_PIN HS Transmit Byte/Word Clock Pin Name Pin name
WORD_CLKOUT_HS_CONN_TYPE HS Transmit Byte/Word Clock Connection Type gclk, rclk
Table 5. MIPI D-PHY TX (Data Lanes) Propertiesn is 0, 1, 2, or 3
API Name GUI Name Values
DIRECTION_PIN Transmit/Receive Direction Pin Name Pin name
ERR_ESC_PIN Escape Entry Error Pin Name Pin name
ERR_CONTROL_PIN Control Error Pin Name Pin name
ERR_CONTENTION_LP0_PIN LP0 Contention Error Pin Name Pin name
ERR_CONTENTION_LP1_PIN LP1 Contention Error Pin Name Pin name
ERR_SYNC_ESC_PIN LP Data Transmit Synchronization Error Pin Name Pin name
FORCE_RX_MODE_PIN Force Receive Mode/Wait For Stop Pin Name Pin name
RX_DATA_ESC_PIN Escape Mode Receive Data [7:0] Bus Name Pin name
RX_LPDT_ESC_PIN Escape LP Data Receive Mode Pin Name Pin name
RX_TRIGGER_ESC_PIN Escape Mode Receive Trigger [3:0] Bus Name Pin name
RX_ULPS_ESC_PIN Escape ULP Receive Mode Pin Name Pin name
RX_VALID_ESC_PIN Escape Mode Receive Data Valid Pin Name Pin name
STOPSTATE_LANn_PIN Stop State Data Lane Pin Name Pin name
TURN_REQUEST_PIN Turnaround Request Pin Name Pin name
TX_REQUEST_ESC_LANn_PIN Escape Mode Transmit Request Pin Name Pin name
TX_REQUEST_HS_LANn_PIN HS Transmit Request and Data Valid Pin Name Pin name
TX_SKEW_CAL_HS_LANn_PIN HS Skew Calibration Pin Name Pin name
TX_READY_HS_LANn_PIN HS Transmit Ready Pin Name Pin name
TX_ULPS_ESC_LANn_PIN ULP Escape Mode State Pin Name Pin name
TX_ULPS_EXIT_LANn_PIN ULP Exit Sequence Pin Name Pin name
TX_ULPS_ACTIVE_NOT_LANn_PIN Active Low ULP State Data Lane Pin Name Pin name
TX_DATA_HS_LANn_PIN HS Transmit Data Bus Name Pin name
TX_WORD_VALID_HS_LANn_PIN HS High Byte Valid Pin Name Pin name
TX_LPDT_ESC_PIN Escape Mode LP Data Pin Name Pin name
TX_VALID_ESC_PIN Escape Mode Data Valid Pin Name Pin name
TX_READY_ESC_PIN Escape Mode Ready Pin Name Pin name
TX_TRIGGER_ESC_PIN Escape Mode Transmit Trigger [3:0] Bus Name Pin name
TX_DATA_ESC_PIN Escape Mode Data [7:0] Bus Name Pin name
1 GUI is available in CLKMUX under Regional Buffers tab.