Synthesis Project Settings

You set project-specific synthesis options in the Project Editor > Synthesis tab.

Table 1. Synthesis Project Settings
Setting	Description
Work Directory	Specify a custom directory or use the default (work_syn).
Generate post synthesis netlist	Choose whether the software should create this netlist. Default: On
Synthesis Options	See Synthesis Options.
Include Dir	Specify directories to include in your project. If you use the IP Manager to add IP, the ip/<module> directory is listed here. The software searches these locations when you use include statements.
Dynamic Parameter	Use this area to add parameters and values that apply to the top-level module or entity in your project. The value passed into the Dynamic Parameter field must be the same format as that you would use for any variable in VHDL or Verilog HDL. For example, string should be in quotation marks.
Verilog `define Macro	Use this area to add `define macros to your project. Some FPGA EDA tools automatically create a SYNTHESIS macro. If you want to use the same behavior in the Efinity software, you need to create it here. For example, click the Add Verilog `define Macro button and then enter `SYNTHESIS` in the NAME field and `1` in the Value field. Then if you want to include simulation only code, use this format: `ifndef SYNTHESIS $display(...) ... some other simulation directives ... `endif You can also use the translate_on and translate_off directives to accomplish similar functionality.