Copy and Paste the Interface Constraints

After you build your interface in the Interface Designer, output the constraints by clicking the Generate Efinity Constraint Files button. The Interface Designer creates the template <design name>.pt.sdc in the outflow directory. You use this template as a blueprint for your own SDC file.
Tip: This file is shown under Interface in the Result pane.

Additionally, you use the <design name>.pt_timing.rpt report for calculating the unsynchronized input and output constraints.

Important: Do not simply add the <design name>.pt.sdc file to your project. This file is a template, and the software overwrites it every time you compile. So any changes you make to it will be lost. Always include your own SDC file in your project, and follow these instructions to copy and paste the interface constraints into it.

To import the constraints into your own SDC file:

  1. Open your SDC file.
  2. Double-click Result > Interface > <project name>.pt.sdc to open the Interface Designer SDC template.
  3. Copy the create_clock constraints for any oscillators or PLLs and paste them into your constraints file. The template file defines a clock period. For example: 
    create_clock -period 8.00 Fclk
create_clock -period 16.00 Sclk
  4. Copy the create_clock constraints for any GPIO clocks. Although the Interface Designer creates a template for them, you need to define the clock period.
    create_clock -period <USER_PERIOD> clk    # template
create_clock -period 10 clk               # added clock period
  5. Copy constraints for the GPIO. The template automatically includes set_input_delay and set_output_delay constraints for all signals and tells you whether you should specify a minimum or maximum value.
    • Copy and paste all of the synchronized constraints into your SDC file without any changes.
    • Copy and paste all of the unsynchronized constraints, and then define them. These constraints are commented out by default.
      Note: Refer to Constraining Unsynchronized Inputs and Outputs for the calculations you use to determine the min and max values.
  6. Save your SDC file and compile your design.

Copy and Paste GPIO Constraints

Copy and paste the synchronized constraints:
set_output_delay -clock Fclk -max -3.903 [get_ports {Fled[0]}]
set_output_delay -clock Fclk -min -1.615 [get_ports {Fled[0]}]
Copy and paste the unsynchronized constraints; they are commented out:
# set_output_delay -clock <CLOCK> -max <MAX CALCULATION> [get_ports {Oled[0]}]
# set_output_delay -clock <CLOCK> -min <MIN CALCULATION> [get_ports {Oled[0]}]
Uncomment and define the unsynchronized constraints:
set_output_delay -clock clk1 -max -7.32 [get_ports {Oled[0]}]
set_output_delay -clock clk1 -min -2.67 [get_ports {Oled[0]}]