VHDL 2019 Support

The Efinity® software supports the interface feature in the VHDL 2019 standard.

Interfaces play a crucial role in hardware design, serving as essential components. Numerous standardized interfaces exist, such as I²C, AXI, or VGA, and user designs incorporate internally developed interfaces to establish connections between different system components. Unfortunately, modeling these interfaces using previous versions of VHDL can be challenging. In most cases, they lack explicit definitions and instead rely on repetitive descriptions within each entity. The only way to identify them is through some naming convention, e.g., all ports of the slave AXI interface could be prefixed with slave_axi_0_.

Due to the absence of a centralized definition and reliance on naming conventions, identifying interfaces within complex entities can be challenging. Not only is the interface repeated in every entity that utilizes it, but it is also replicated in each instantiation. Maintaining this duplicated code becomes burdensome. For instance, modifying the type or name of an interface element requires edits in numerous files, even in architectures that solely pass the interface to an instantiation. Because the VHDL language prioritizes strong typing and early bug detection, the interface feature has been added to VHDL-2019.