PCIe Property Reference

These PCIe block properties are only applicable to Titanium s with transceivers. Refer to the data sheet for which packages have transceivers.

Table 1. Base Properties
API Name GUI Name Values
NAME Instance Name Instance name
RESOURCE PCIe Resource Resource
PIPE_CONFIG_CMN__CONFIG_REG_0__MODE_SELECT Mode Endpoint, Root Port
PIPE_CONFIG_CMN__CONFIG_REG_0__LANE_COUNT_IN Link Width x4, x2, x1
PIPE_CONFIG_CMN__CONFIG_REG_0__PCIE_GENERATION_SEL Generation Gen4, Gen3, Gen2, Gen1
SS_PCIE_MPS (endpoint)
I_CLIENT_RC__I_PCIE_CAP__MP (root port)
 Maximum Payload Size 128 bytes, 256 bytes, 512 bytes
SS_PCIE_GEN4_TX_PRESET Gen4 Equalization TX Preset 0 - 0xA
SS_PCIE_GEN3_RX_PRESET Gen3 Equalization RX Preset 0 - 0x6
SS_PCIE_GEN3_TX_PRESET Gen3 Equalization TX Preset 0 - 0xA
SS_PCIE_SRIS_EN SRIS Enable 0, 1
SS_PCIE_COMPLIANCE_EN Force device to enter compliance mode 0, 1
Table 2. Reference Clock Properties
API Name GUI Name Values
REF_CLK_FREQUENCY Reference Clock Frequency 100.0
PIPE_CONFIG_CMN__CONFIG_REG_2__PMA_CMN_REFCLK_SEL Reference Clock Source Type External
PMA_CMN__CMN_PLLLC_GEN_PREG__CMN_PLLLC_PFDCLK1_SEL_PREG External Clock Refclk 0
PIPE_CONFIG_CMN__CONFIG_REG_2__PMA_CMN_REFCLK_TERMEN Enable 50 Ω to ground on-die termination for REFCLK0 0, 1
SS_REFCLK_ONBOARD_OSC Reference clock from on-board crystal 0, 1
Table 3. Reset Properties
API Name GUI Name Values
HOT_RESET_IN_PIN Hot Reset Input Pin Name Pin name
HOT_RESET_OUT_PIN Hot Reset Output Pin Name Pin name
LINK_DOWN_RESET_OUT_PIN Link Down Reset Pin Name Pin name
RESET_ACK_PIN Reset Acknowledge Pin Name Pin name
RESET_REQ_PIN Reset Request Pin Name Pin name
Table 4. Function Properties
API Name GUI Name Values
PIPE_CONFIG_CMN__CONFIG_REG_​0__ARI_ENABLE ARI Enable 0, 1
I_CLIENT_LM__I_RC_BAR_CONFIG_​REG__RCBAR0A BAR0 Aperture '1 GB','1 KB','1 MB','128 B','128 GB','128 KB','128 MB','16 B','16 GB','16 KB','16 MB','2 GB','2 KB','2 MB','256 B','256 GB','256 KB','256 MB','32 B','32 GB','32 KB','32 MB','4 B','4 GB','4 KB','4 MB','512 B','512 KB','512 MB','64 B','64 GB','64 KB','64 MB','8 B','8 GB','8 KB','8 MB'
I_CLIENT_LM__I_RC_BAR_CONFIG_​REG__RCBAR0C BAR0 Control '32 bit I/O BAR','32 bit non-prefetchable memory BAR','32 bit prefetchable memory BAR','64 bit non-prefetchable memory BAR','64 bit prefetchable memory BAR','Disabled'
I_CLIENT_LM__I_RC_BAR_CONFIG_​REG__RCBAR1A BAR1 Aperture '1 GB','1 KB','1 MB','128 B','128 KB','128 MB','16 B','16 KB','16 MB','2 GB','2 KB','2 MB','256 B','256 KB','256 MB','32 B','32 KB','32 MB','4 B','4 KB','4 MB','512 B','512 KB','512 MB','64 B','64 KB','64 MB','8 B','8 KB','8 MB'
I_CLIENT_LM__I_RC_BAR_CONFIG_​REG__RCBAR1C BAR1 Control '32 bit I/O BAR','32 bit non-prefetchable memory BAR','32 bit prefetchable memory BAR','Disabled'
PIPE_CONFIG_CMN__CONFIG_REG_​0__SR_IOV_ENABLE Enable SRIOV 0, 1
I_CLIENT_PF0__I_FUNC_DEP_LINK_​NUMVFS_REG__NVF PF0 VF Count 0 - 64
I_CLIENT_PF1__I_FUNC_DEP_LINK_​NUMVFS_REG__NVF PF1 VF Count 0 - 64
I_CLIENT_PF2__I_FUNC_DEP_LINK_​NUMVFS_REG__NVF PF2 VF Count 0 - 64
I_CLIENT_PF3__I_FUNC_DEP_LINK_​NUMVFS_REG__NVF PF3 VF Count 0 - 64
I_CLIENT_LM__I_VENDOR_ID_REG__VID Subsystem Vendor ID 0 - 0xFFFF
I_CLIENT_LM__I_VENDOR_ID_REG__SVID Vendor ID 0 - 0xFFFF
SS_PCIE_PF_NUM Total Physical Functions 1 - 4
I_CLIENT_RC__I_VENDOR_ID_DEVICE_​ID__DID Device ID 0 - 0xFFFF
I_CLIENT_RC__I_REVISION_ID_CLASS_​CODE__RID Revision ID 0 - 0xFF
I_CLIENT_RC__I_REVISION_ID_CLASS_​CODE__PIB Class Code 0 - 0xFF
I_CLIENT_RC__I_REVISION_ID_CLASS_​CODE__SCC Sub-Class Code 0 - 0xFF
I_CLIENT_RC__I_REVISION_ID_CLASS_​CODE__CC Programming Interface Byte 0 - 0xFF
Table 5. Physical Functions n PropertiesWhere n is 0, 1, 2, or 3
API Name GUI Name Values
I_CLIENT_PFn__I_VENDOR_ID_DEVICE_ID__DID Device ID 0 - 0xFFFF
SS_PCIE_PFn_EXP_ROM_BAR Expansion ROM BAR Aperture 2 KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, 256 KB, 512 KB, 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, Disabled
I_CLIENT_PFn__I_REVISION_ID_CLASS_CODE__RID Revision ID 0 - 0xFF
I_CLIENT_PFn__I_REVISION_ID_CLASS_CODE__CC Class Code 0 - 0xFF
I_CLIENT_PFn__I_REVISION_ID_CLASS_CODE__SCC Sub-Class Code 0 - 0xFF
I_CLIENT_PFn__I_MSIX_TBL_OFFSET__BARI MSI-X BAR Indicator BAR0, BAR1, BAR2, BAR3, BAR4, BAR5
I_CLIENT_PFn__I_MSIX_PENDING_INTRPT__BARI1 MSI-X PBA Indicator BAR0, BAR1, BAR2, BAR3, BAR4, BAR5
I_CLIENT_PFn__I_MSIX_PENDING_INTRPT__PBAO MSI-X PBA Offset 0x0 - 0x1FFFFFFF
I_CLIENT_PFn__I_MSIX_TBL_OFFSET__TO MSI-X Table Offset 0x0 - 0x1FFFFFFF
I_CLIENT_PFn__I_MSIX_CTRL__MSIXTS MSI-X Table Size 0x0 - 0x7FF
I_CLIENT_PFn__I_MSIX_CTRL__CID MSI-X Capability ID 0x0 - 0xFF
I_CLIENT_PFn__I_MSIX_CTRL__CP MSI-X Capabilities Pointer 0x0 - 0xFF
I_CLIENT_PFn__I_REVISION_ID_CLASS_CODE__PIB Programming Interface Byte 0 - 0xFF
I_CLIENT_LM__I_PF_n_BAR_CONFIG_1_REG__ERBC Resizable BAR Enable 0, 1
I_CLIENT_PFn__I_SUBSYSTEM_VENDOR_ID_​SUBSYSTEM_I__SID Subsystem ID 0 - 0xFF
I_CLIENT_LM__I_PF_n_BAR_CONFIG_0_REG__BAR0C BAR0 Control Disabled
32 bit I/O BAR
32 bit non-prefetchable memory BAR
32 bit prefetchable memory BAR
64 bit non prefetchable memory BAR
64 bit prefetchable memory BAR
I_CLIENT_LM__I_PF_n_BAR_CONFIG_0_REG__BAR0A BAR0 Aperture 128 B, 256 B, 512 B, 1 KB, 2 KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, 256 KB, 512 KB, 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB
I_CLIENT_LM__I_PF_n_BAR_CONFIG_0_REG__BAR1C BAR1 Control Disabled
32 bit I/O BAR
32 bit non-prefetchable memory BAR
32 bit prefetchable memory BAR
I_CLIENT_LM__I_PF_n_BAR_CONFIG_0_REG__BAR1A BAR1 Aperture 128 B, 256 B, 512 B, 1 KB, 2 KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, 256 KB, 512 KB, 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB, 256 MB, 512 MB, 1 GB, 2 GB
I_CLIENT_LM__I_PF_n_BAR_CONFIG_0_REG__BAR2C BAR2 Control Disabled
32 bit I/O BAR
32 bit non-prefetchable memory BAR
32 bit prefetchable memory BAR
64 bit non prefetchable memory BAR
64 bit prefetchable memory BAR
I_CLIENT_LM__I_PF_n_BAR_CONFIG_0_REG__BAR2A BAR2 Aperture 128 B, 256 B, 512 B, 1 KB, 2 KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, 256 KB, 512 KB, 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB
I_CLIENT_LM__I_PF_n_BAR_CONFIG_0_REG__BAR3C BAR3 Control Disabled
32 bit I/O BAR
32 bit non-prefetchable memory BAR
32 bit prefetchable memory BAR
I_CLIENT_LM__I_PF_n_BAR_CONFIG_0_REG__BAR3A BAR3 Aperture 128 B, 256 B, 512 B, 1 KB, 2 KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, 256 KB, 512 KB, 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB, 256 MB, 512 MB, 1 GB, 2 GB
I_CLIENT_LM__I_PF_n_BAR_CONFIG_1_REG__BAR4C BAR4 Control Disabled
32 bit I/O BAR
32 bit non-prefetchable memory BAR
32 bit prefetchable memory BAR
64 bit non prefetchable memory BAR
64 bit prefetchable memory BAR
I_CLIENT_LM__I_PF_n_BAR_CONFIG_1_REG__BAR4A BAR4 Aperture 128 B, 256 B, 512 B, 1 KB, 2 KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, 256 KB, 512 KB, 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB
I_CLIENT_LM__I_PF_n_BAR_CONFIG_1_REG__BAR5C BAR5 Control Disabled
32 bit I/O BAR
32 bit non-prefetchable memory BAR
32 bit prefetchable memory BAR
I_CLIENT_LM__I_PF_n_BAR_CONFIG_1_REG__BAR5A BAR5 Aperture 128 B, 256 B, 512 B, 1 KB, 2 KB, 4 KB, 8 KB, 16 KB, 32 KB, 64 KB, 128 KB, 256 KB, 512 KB, 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB, 256 MB, 512 MB, 1 GB, 2 GB
I_CLIENT_PFn__I_MSI_CTRL_REG__MMC MSI Multiple Message Capable 1, 2, 4, 8, 16, 32
SS_PCIE_PFn_LEGACY_INT_PIN Interrupt Pin INTA, INTB, INTC, INTD, NO INT
I_CLIENT_PFn__I_VENDOR_SPECIFIC_HEADER_REG​__VI User ID register from Vendor Specific Extended Capability 0x0:0xffff
Table 6. Physical Function n - Virtual Function
API Name GUI Name Values
SS_PCIE_PFn_VF_ATS_EN ATS Enable 0, 1
SS_PCIE_PFn_VF_TPH_EN Enable TPH 0, 1
SS_PCIE_PFn_VF_MSI_MUL_MESSAGE_CAP MSI Multiple Message Capable 1, 16, 2, 32, 4, 8
SS_PCIE_PFn_VF_MSIX_BAR_IND MSI-X BAR Indicator 'BAR0', 'BAR1', 'BAR2', 'BAR3', 'BAR4', 'BAR5'
SS_PCIE_PFn_VF_MSIX_PBA_IND MSI-X PBA Indicator 'BAR0', 'BAR1', 'BAR2', 'BAR3', 'BAR4', 'BAR5'
SS_PCIE_PFn_VF_MSIX_PBA_OFFSET MSI-X PBA Offset 0x0 - 0x1fffffff
SS_PCIE_PFn_VF_MSIX_TABLE_OFFSET MSI-X Table Offset 0x0 - 0x1fffffff
SS_PCIE_PFn_VF_MSIX_TABLE_SIZE MSI-X Table Size 0x0 - 0x7ff
SS_PCIE_PFn_VF_STEERING_TAG_TAB_LOC Steering Tag Table Location 'ST Table in the TPH Requester Capability Structure', 'ST Table not present', 'ST values stored in the MSI-X Table in client RAM'
SS_PCIE_PFn_VF_STEERING_TAG_TAB_SIZE Steering Tag Table Size 0 - 2047
SS_PCIE_PFn_VF_SUBSYSTEM_ID Subsystem ID 0x0 - 0xffff
I_CLIENT_LM__I_PF_n_VF_BAR_CONFIG_0_REG__VFBAR0A VF BAR0 Aperture '1 GB', '1 KB', '1 MB', '128 B', '128 GB', '128 KB', '128 MB', '16 GB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 GB', '256 KB', '256 MB', '32 GB', '32 KB', '32 MB', '4 GB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 GB', '64 KB', '64 MB', '8 GB', '8 KB', '8 MB'
I_CLIENT_LM__I_PF_n_VF_BAR_CONFIG_0_REG__VFBAR0C VF BAR0 Control '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', '64 bit non-prefetchable memory BAR', '64 bit prefetchable memory BAR', 'Disabled'
I_CLIENT_LM__I_PF_n_VF_BAR_CONFIG_0_REG__VFBAR1A VF BAR1 Aperture '1 GB', '1 KB', '1 MB', '128 B', '128 KB', '128 MB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 KB', '256 MB', '32 KB', '32 MB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 KB', '64 MB', '8 KB', '8 MB'
I_CLIENT_LM__I_PF_n_VF_BAR_CONFIG_0_REG__VFBAR1C VF BAR1 Control '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', 'Disabled'
I_CLIENT_LM__I_PF_n_VF_BAR_CONFIG_0_REG__VFBAR2A VF BAR2 Aperture '1 GB', '1 KB', '1 MB', '128 B', '128 GB', '128 KB', '128 MB', '16 GB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 GB', '256 KB', '256 MB', '32 GB', '32 KB', '32 MB', '4 GB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 GB', '64 KB', '64 MB', '8 GB', '8 KB', '8 MB'
I_CLIENT_LM__I_PF_n_VF_BAR_CONFIG_0_REG__VFBAR2C VF BAR2 Control '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', '64 bit non-prefetchable memory BAR', '64 bit prefetchable memory BAR', 'Disabled'
I_CLIENT_LM__I_PF_n_VF_BAR_CONFIG_0_REG__VFBAR3A VF BAR3 Aperture '1 GB', '1 KB', '1 MB', '128 B', '128 KB', '128 MB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 KB', '256 MB', '32 KB', '32 MB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 KB', '64 MB', '8 KB', '8 MB'
I_CLIENT_LM__I_PF_n_VF_BAR_CONFIG_0_REG__VFBAR3C VF BAR3 Control '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', 'Disabled'
I_CLIENT_LM__I_PF_n_VF_BAR_CONFIG_1_REG__VFBAR4A VF BAR4 Aperture '1 GB', '1 KB', '1 MB', '128 B', '128 GB', '128 KB', '128 MB', '16 GB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 GB', '256 KB', '256 MB', '32 GB', '32 KB', '32 MB', '4 GB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 GB', '64 KB', '64 MB', '8 GB', '8 KB', '8 MB'
I_CLIENT_LM__I_PF_n_VF_BAR_CONFIG_1_REG__VFBAR4C VF BAR4 Control '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', '64 bit non-prefetchable memory BAR', '64 bit prefetchable memory BAR', 'Disabled'
I_CLIENT_LM__I_PF_n_VF_BAR_CONFIG_1_REG__VFBAR5A VF BAR5 Aperture '1 GB', '1 KB', '1 MB', '128 B', '128 KB', '128 MB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 KB', '256 MB', '32 KB', '32 MB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 KB', '64 MB', '8 KB', '8 MB'
I_CLIENT_LM__I_PF_n_VF_BAR_CONFIG_1_REG__VFBAR5C VF BAR5 Control '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', 'Disabled'
Table 7. BAR0 Address Translation
API Name GUI Name Values
Table 8. BAR1 Address Translation
API Name GUI Name Values
Table 9. RP Outbound
API Name GUI Name Values
Table 10. Device Capability
API Name GUI Name Values
I_CLIENT_PF0__I_DEV_SER_NUM_0​__DSND0 Device Serial Number (DW1) 0x0 - 0xFFFFFFFF
I_CLIENT_PF0__I_DEV_SER_NUM_1​__DSND1 Device Serial Number (DW2) 0x0 - 0xFFFFFFFF
I_CLIENT_PF0__I_LINK_CTRL_STATUS​__SCC Enable Slot Clock Configuration 0, 1
I_CLIENT_PF0__I_PCIE_DEV_CTRL_STATUS​__ETFE Extended Tag Field 0, 1
Table 11. Slot Capability
API Name GUI Name Values
Table 12. AXI General Properties
API Name GUI Name Values
AXI_MASTER_EN Enable AXI Master Interface 0, 1
AXI_SLAVE_EN Enable AXI Slave Interface 0, 1
AXI_CLK_PIN AXI Clock Pin Name Pin name
AXI_CLK_INVERT_EN Invert AXI Clock Pin 0, 1
USER_AXI_RESET_N_PIN AXI Reset (Active-Low) Pin Name Pin name
Table 13. AXI Master/Slave Read Address Channel PropertiesWhere tm is TARGET or MASTER
API Name GUI Name Values
tm_AXI_ARID_PIN Address ID [5:0] Bus Name Bus name
tm_AXI_ARREADY_PIN Address Ready Pin Name Pin name
tm_AXI_ARVALID_PIN Address Valid Pin Name Pin name
tm_AXI_ARLEN_PIN Burst Length [7:0] Bus Name Bus name
tm_AXI_ARSIZE_PIN Burst Size [2:0] Bus Name Bus name
tm_AXI_ARUSER_PIN Read Address User [87:0] Bus Name Bus name
tm_AXI_ARADDR_PIN Read Address [63:0] Bus Name Bus name
Table 14. AXI Master/Slave Write Address Channel PropertiesWhere tm is TARGET or MASTER
API Name GUI Name Values
tm_AXI_AWID_PIN Address ID [5:0] Bus Name Bus name
tm_AXI_AWREADY_PIN Address Ready Pin Name Pin name
tm_AXI_AWVALID_PIN Address Valid Pin Name Pin name
tm_AXI_AWLEN_PIN Burst Length [7:0] Bus Name Bus name
tm_AXI_AWSIZE_PIN Burst Size [2:0] Bus Name Bus name
tm_AXI_AWUSER_PIN Write Address User [87:0] Bus Name Bus name
tm_AXI_AWADDR_PIN Write Address [32:0] Bus Name Bus name
Table 15. AXI Master/Slave Write Response Channel PropertiesWhere tm is TARGET or MASTER
API Name GUI Name Values
tm_AXI_BID_PAR_PIN Response ID Tag Parity Pin Name Pin name
tm_AXI_BID_PIN Response ID Tag [7:0] Bus Name Bus name
tm_AXI_BREADY_PIN Response Ready Pin Name Pin name
tm_AXI_BRESP_PAR Write Response Parity Pin Name Pin name
tm_AXI_BVALID_PIN Write Response Valid Pin Name Pin name
tm_AXI_BRESP_PIN Write Response [1:0] Bus Name Bus name
Table 16. AXI Master/Slave Read Data Channel PropertiesWhere tm is TARGET or MASTER
API Name GUI Name Values
tm_AXI_RDATA_PAR_PIN Read Data Parity [31:0] Bus Name Bus name
tm_AXI_RDATA_PIN Read Data Bus Name Bus name
tm_AXI_RID_PAR_PIN Read ID Tage Parity Pin Name Pin name
tm_AXI_RID_PIN Read ID Tag [7:0] Bus Name Bus name
tm_AXI_RLAST_PIN Read Last Pin Name Pin name
tm_AXI_RREADY_PIN Read Ready Pin Name Pin name
tm_AXI_RRESP_PIN Read Response Bus Name Bus name
tm_AXI_RVALID_PIN Read Valid Pin Name Pin name
Table 17. AXI Master/Slave Write Data Channel PropertiesWhere tm is TARGET or MASTER
API Name GUI Name Values
tm_AXI_WREADY_PIN Address Ready Pin Name Pin name
tm_AXI_WDATA_PAR_PIN Write Data Parity [31:0] Bus Name Bus name
tm_AXI_WDATA_PIN Write Data [255:0] Bus Name Bus name
tm_AXI_WLAST_PIN Write Last Pin Name Pin name
tm_AXI_WSTRB_PAR_PIN Write Strobes Parity [3:0] Bus Name Bus name
tm_AXI_WSTRB_PIN Write Strobes [31:0] Bus Name Bus name
tm_AXI_WVALID_PIN Write Valid Pin Name Pin name
Table 18. AXI Master Sideband Properties
API Name GUI Name Values
TARGET_NON_POSTED_REJ_PIN Non-Posted TLP Pin Name Pin name
Table 19. Interrupt Properties
API Name GUI Name Values
INTERRUPT_EN Enable Interrupt 0, 1
INTERRUPT_SIDEBAND_SIGNALS_PIN Interrupt Sideband Signals [27:0] Bus Name Bus name
LOCAL_INTERRUPT_PIN Local Error and Status Register Interrupt Pin Name Pin name
Table 20. Legacy Interrupt Properties
API Name GUI Name Values
INTA_OUT_PIN INTA Output Pin Name Pin name
INTB_OUT_PIN INTB Output Pin Name Pin name
INTC_OUT_PIN INTC Output Pin Name Pin name
INTD_OUT_PIN INTD Output Pin Name Pin name
INT_ACK_PIN INTx Acknowledge Pin Name Pin name
INTA_IN_PIN Interrupt Input A Pin Name Pin name
INTB_IN_PIN Interrupt Input B Pin Name Pin name
INTC_IN_PIN Interrupt Input C Pin Name Pin name
INTD_IN_PIN Interrupt Input D Pin Name Pin name
INT_PENDING_STATUS_PIN Interrupt Pending Status [3:0] Bus Name Bus name
Table 21. MSI Properties
API Name GUI Name Values
MSI_EN Enable MSI 0, 1
PF0_MSI_PENDING_STATUS_IN_PIN PF0 MSI Pending Status Input [31:0] Bus Name Bus name
PF1_MSI_PENDING_STATUS_IN_PIN PF1 MSI Pending Status Input [31:0] Bus Name Bus name
PF2_MSI_PENDING_STATUS_IN_PIN PF2 MSI Pending Status Input [31:0] Bus Name Bus name
PF3_MSI_PENDING_STATUS_IN_PIN PF3 MSI Pending Status Input [31:0] Bus Name Bus name
Table 22. Message Properties
API Name GUI Name Values
MSG_BYTE_EN_PIN Message Byte Enable [31:0] Bus Name Bus name
MSG_DATA_PIN Message Data Indication Pin Name Pin name
MSG_END_PIN Message End Pin Name Pin name
MSG_PASID_PRESENT_PIN Message PASID Present Pin Name Pin name
MSG_PASID_PIN Message PASID [21:0] Bus Name Bus name
MSG_START_PIN Message Start Pin Name Pin name
MSG_VALID_PIN Message Valid Pin Name Pin name
MSG_VDH_PIN Message Vendor Defined Header Pin Name Pin name
MSG_PIN Message [255:0] Bus Name Bus name
Table 23. Error Indicator Properties
API Name GUI Name Values
CORRECTABLE_ERROR_IN_PIN Correctable Error Input Pin Name Pin name
CORRECTABLE_ERROR_OUT_PIN Correctable Error Output Pin Name Pin name
FATAL_ERROR_OUT_PIN Fatal Error Output Pin Name Pin name
NON_FATAL_ERROR_OUT_PIN Non-Fatal Error Output Pin Name Pin name
PHY_INTERRUPT_OUT_PIN PHY Interrupt Output Pin Name Pin name
UNCORRECTABLE_ERROR_IN_PIN Uncorrectable Error Input Pin Name Pin name
Table 24. APB Properties
API Name GUI Name Values
USER_APB_PADDR_PIN APB Address [23:0] Bus Name Bus name
USER_APB_PENABLE_PIN APB Enable Pin Name Pin name
USER_APB_CLK_PIN APB Interface Clock Pin Name Pin name
USER_APB_CLK_INVERT_EN Invert APB Interface Clock Pin 0, 1
USER_APB_PRDATA_PAR_PIN APB Read Data Parity [3:0] Bus Name Bus name
USER_APB_PRDATA_PIN APB Read Data [31:0] Bus Name Bus name
USER_APB_PREADY_PIN APB Ready Pin Name Pin name
USER_APB_PSEL_PIN APB Select Pin Name Pin name
USER_APB_PSTRB_PAR_PIN APB Strobe Parity Pin Name Pin name
USER_APB_PSTRB_PIN APB Strobe [3:0] Bus Name Bus name
USER_APB_PWDATA_PAR_PIN APB Write Data Parity [3:0] Bus Name Bus name
USER_APB_PWDATA_PIN APB Write Data[31:0] Bus Bane Bus name
USER_APB_PWRITE_PIN APB Write/Read Access Pin Name Pin name
Table 25. Function Level Reset Properties
API Name GUI Name Values
FLR_IN_PROGRESS_PIN FLR In Progress [3:0] Bus Name Bus name
FLR_DONE_PIN Function Level Reset (FLR) Done [3:0] Bus Name Bus name
VF_FLR_IN_PROGRESS_PIN VF FLR In Progress [63:0] Bus Name Bus name
VF_FLR_DONE_PIN Virtual Function FLR Done [63:0] Bus Name Bus name
Table 26. Status Properties
API Name GUI Name Values
STATUS_EN Enable Status 0, 1
REG_ACCESS_CLK_SHUTOFF_PIN APB Access Clock Shutoff Pin Name Pin name
CORE_CLK_SHUTOFF_PIN Core Clock Shutoff Pin Name Bus name
FUNCTION_STATUS_PIN Function Status [15:0] Bus Name Bus name
LTSSM_STATE_PIN LTSSM State [5:0] Bus Name Bus name
LINK_STATUS_PIN PCIe Link Status [1:0] Bus Name Bus name
PCIE_MAX_PAYLOAD_SIZE_PIN PCIe Maximum Payload Size [2:0] Bus Name Bus name
PCIE_MAX_READ_REQ_SIZE_PIN PCIe Maximum Read Request Size [2:0] Bus Name Bus name
PIPE_P00_RATE_PIN PIPE P00 Rate [1:0] Bus Name Bus name
PMA_CMN_READY_PIN Ready Pin Name Pin name
Table 27. Configuration Snoop Properties
API Name GUI Name Values
CFG_SNOOP_EN Enable Configuration Snoop 0, 1
CONFIG_FUNCTION_NUM_PIN Configuration Function Number [7:0] Bus Name Bus name
CONFIG_READ_DATA_PAR_PIN Configuration Read Data Parity [3:0] Bus Name Bus name
CONFIG_READ_DATA_VALID_PIN Configuration Read Data Valid Pin Name Pin name
CONFIG_READ_DATA_PIN Configuration Read Data [31:0] Bus Name Bus name
CONFIG_READ_RECEIVED_PIN Configuration Read Received Pin Name Pin name
CONFIG_REG_NUM_PIN Configuration Register Address [9:0] Bus Name Bus name
CONFIG_WRITE_BYTE_ENABLE_PAR_PIN Configuration Write Byte Enable Parity Pin Name Pin name
CONFIG_WRITE_BYTE_ENABLE_PIN Configuration Write Byte Enable [3:0] Bus Name Bus name
CONFIG_WRITE_DATA_PAR_PIN Configuration Write Data Parity [3:0] Bus Name Bus name
CONFIG_WRITE_DATA_PIN Configuration Write Data [31:0] Bus Name Bus name
CONFIG_WRITE_RECEIVED_PIN Configuration Write Received Pin Name Pin name
Table 28. Power Management Properties
API Name GUI Name Values
I_CLIENT_PF0__I_L1_PM_CTRL_1__L1PML11EN PM L1.1 Substate Enable 0, 1
I_CLIENT_PF0__I_L1_PM_CTRL_1__L1PML12EN PM L1.2 Substate Enable 0, 1
SS_PCIE_ASPM (endpoint)
I_CLIENT_RC__I_LINK_CTRL_STATUS__ASPMC (root port)
 ASPM Enable Disabled, L0s Entry, L1 Entry, L0s and L1 Entry
I_CLIENT_RC__I_L1_PM_CTRL_1__L1PML11EN PM L1.1 Substate Enable 0, 1
I_CLIENT_RC__I_L1_PM_CTRL_1__L1PML12EN PM L1.2 Substate Enable 0, 1
I_CLIENT_RC__I_L1_PM_CTRL_1__L1ASPML11EN ASPM L1.1 Substate Enable 0, 1
I_CLIENT_RC__I_L1_PM_CTRL_1__L1ASPML12EN ASPM L1.2 Substate Enable 0, 1
I_CLIENT_PF0__I_L1_PM_CTRL_1__L1ASPML11EN ASPM L1.1 Substate Enable 0, 1
I_CLIENT_PF0__I_L1_PM_CTRL_1__L1ASPML12EN ASPM L1.2 Substate Enable 0, 1
I_CLIENT_RC__I_L1_PM_CTRL_1__L1ASPML11EN ASPM L1.1 Substate Enable 0, 1
I_CLIENT_RC__I_L1_PM_CTRL_1__L1ASPML12EN ASPM L1.2 Substate Enable 0, 1
PWR_MGMT_EN Enable Power Management 0, 1
PMCLK_CONN_TYPE Power Management Clock Connection Type gclk, rclk
PM_CLK_PIN Power Management Clock Pin Name Pin name
DPA_INTERRUPT_PIN Dynamic Power Allocation Interrupt [3:0] Bus Name Bus name
CLIENT_REQ_EXIT_L2_PIN Exit L2 Request Pin Name Pin name
CLIENT_REQ_EXIT_L1_PIN L1 Exit Request Pin Name Pin name
PCIE_LINK_POWER_STATE_PIN PCIe Link Power State [3:0] Bus Name Bus name
POWER_STATE_CHANGE_ACK_PIN Power State Change Acknowledge Pin Name Pin name
POWER_STATE_CHANGE_FUNCTION_NUM_PIN Power State Change Function [7:0] Bus Name Bus name
POWER_STATE_CHANGE_INTERRUPT_PIN Power State Change Interrupt Pin Name Pin name
FUNCTION_POWER_STATE_PIN Power State Function [11:0] Bus Name Bus name
REQ_PM_TRANSITION_L23_READY_PIN Transition PM to L23_READY Request Pin Name Pin name
Table 29. L1 Substate Properties
API Name GUI Name Values
CLKREQ_IN_N_PIN Clock Request Input (Active-Low) Pin Name Pin name
CLKREQ_OUT_N_PIN Clock Request Output (Active-Low) Pin Name Pin name
L1_PM_SUBSTATE_OUT_PIN L1 PM Substate [2:0] Bus Name Bus name
CLIENT_REQ_EXIT_L1_SUBSTATE_PIN L1-Substate Exit Request Pin Name Pin name