Common Mistakes

This topic describes some common mistakes that affect timing.

Latches and Combinational Loops

If you do not assign an output for all possible conditions in an if or case statement (that is, incomplete assignment), the software infers a latch. Trion®, Topaz, and Titanium FPGAs do not support latches natively in hardware. The Efinity® synthesis tool infers look-up tables (LUTs) to provide latch behaviour.

You also may create a latch accidentally when you meant to use a flipflop. From a timing perspective, the latch causes a combinational loop and the timing graph cannot have a loop. Therefore, if the software detects a combinational loop it cuts the loop at an arbitrary point.

To resolve this issue, make sure if and case statements are complete and use flipflops instead of latches.

Unintended Virtual Clock

If you create a clock with the -name option without a target (e.g., get_ports), you create a virtual clock. Make sure to use a target unless you really want a virtual clock. 

create_clock -period 40 -name clk_in [get_ports clk_in]    # defined clock
create_clock -period 40 -name virtual_clk                  # virtual clock

The Efinity software prints an info message when it finds a virtual clock definition so you can double check your constraints. See Virtual Clocks for more information.

Undefined Clocks

If you have an SDC file and do not define all clocks, the software cannot perform timing analysis on any logic controlled by those clocks. This situation leads to unoptimized results. Therefore, you should always define all clocks in your design.

Incorrect Constraint Order

The order of constraints in the SDC file is important. If you use the wrong order you get unintended results. For example, always define a clock before using set_input_delay or set_output_delay constraints for that clock. Refer to About SDC Files for more information about the expected constraint order.