About SDC Files

An SDC file is simply a text file with one constraint per line; however, you need to keep some rules in mind when creating it:
  • The order of the constraints in the SDC file is important. If there are dependencies between any of the constraints, you must ensure that you have written them in the correct order for them to be valid.
  • If a constraint has incorrect syntax, the software ignores it and issues a warning message.
  • For some constraints, the argument order is important for the constraint to be valid.
  • The minimum content required in an SDC file is a create_clock constraint. You should always set a clock constraint—even if it is a virtual clock—whenever you create an SDC file.
Important: SDC is case sensitive. If you are using VHDL, which is not case sensitive, be careful when declaring net names. The Efinity software converts all names to lowercase letters during synthesis. Therefore, the SDC should use lowercase letters not mixed case or uppercase.

If you do not define an SDC file, the software defaults to creating clocks with a period of 1 ns for every clock source in your design and does not constrain any I/O pins. It assumes that all of the clocks it finds are related. The Efinity® timing analyzer then identifies the critical path based on this default constraint.

Constraint Order

First, define the clocks and other timing assertions in this order:

  1. Primary clocks
  2. Virtual clocks
  3. Generated clocks
  4. Clock groups
  5. Input and output delays

Then, define any timing exceptions, in this order:

  1. False paths
  2. Maximum and minimum delays
  3. Multicycle paths