Tools for Exploring Timing

You use static timing analysis (STA) to measure the timing performance of your design. The software generates a timing report based on the design’s place and route results and the project’s SDC file. The software provides several tools for viewing and cross-probing timing results:

  • The Timing Browser helps you explore your design’s critical paths and the cells of those paths.
  • The Floorplan tool shows the locations of the paths and cells in the fabric.
  • The Tcl Console helps you analyze and explore timing.

The Efinity software uses a Tcl interpreter to process SDC constraints and to support timing analysis. The Tcl Console is an interactive shell that you use to execute Tcl commands. Refer to Tcl Console for details on using the console in the Efinity GUI or in a terminal.

The software displays Tcl reports in the Timing Browser.

  • Click on the report name to view details.
  • Click on cell names under Data Path Cell to view the location of the cell in the Floorplan Editor.
  • Turn on Show Timing Path or Show Timing Delay in the Floorplan Editor to see the path and delay for a particular cell.
Figure 1. Using the Timing Browser
Note: Refer to Tcl Console for more information on available commands. For help on available Tcl commands, type help -category <sdc or timing> in the Tcl Command Console.