set_input_delay and set_output_delay Constraints

set_input_delay -clock <clock> [clock_fall] [-max] [-min] <delay> [-reference_pin] \
   <ports> [-add_delay]
set_output_delay -clock <clock> [clock_fall] [-max] [-min] <delay> [-reference_pin] \
   <ports> [-add_delay]
  • Use set_input_delay to analyze timing paths from input I/Os.
  • Use set_output_delay for timing paths to output I/Os. If you do not specify these commands in your SDC, paths from and to I/Os will not be analyzed.

These commands constrain each I/O pad specified to be timing-equivalent to a register clocked on the clock specified after -clock. This register can be either a clock signal in your design or a virtual clock that does not exist in the design but that you use to specify the I/O timing.

The command also adds <delay> through each pad, thereby tightening the time constraint along paths traveling through the I/O pad. You can use this additional delay to model board-level delays. -max is the setup constraint, -min is the hold constraint; if you specify neither, the tool uses <delay> for both max and min.

  • -clock is the clock name
  • -clock_fall is the input delay relative to the clock’s falling edge
  • -max is the maximum data arrival time
  • -min is the minimum data arrival time
  • <delay> is the delay value
  • -reference_pin is an optional flag to include the clock delay to the pin when calculating the input or output delay (Titanium and Topaz only). When you generate constraints in the Interface Designer, the software automatically includes this option for synchronous interface signals (such as GPIO or LVDS).
  • <ports> is the list of input or output ports
  • -add_delay specifies any additional delay or clock condition for the port. If you do not specify this option, then any latter set_input_delay or set_output_delay command replaces the prior commands.

See Constraining I/O.