PLL Local Feedback Clock Latency

When using a PLL as a clock source you need to account for the any board delay, the GPIO input buffer delay (for the PLL's reference clock pin), and the PLL compensation delay.

When the PLL is in local feedback mode, the compensation delay is zero.

Figure 1. PLL Local Feedback Mode Delay

The SDC constraint formulas for the receive clock delay are:

set_clock_latency -source -setup <max calculation> <clock ports>
set_clock_latency -source -hold <min calculation> <clock ports>

The equations are:

<max calculation> = <max board constraint> + GPIO_INmax - <PLL compensation>

<min calculation> = <min board constraint> + GPIO_INmin - <PLL compensation>

The Efinity software v2023.2 and higher calculates the GPIO input buffer and PLL compensation delays and provides them in a template in the <project>.pt.sdc file. You still need to add any board delays if needed.

The following example shows how to calculate the delays and set the constraints.

Setting PLL Local Feedback Clock Latency

In this example, the PLL clock output is called clk. This example assumes that the clock and data traces on the board are well matched; therefore, there is no external board delay.
For the GPIO_IN delays, this example uses the values for the i pin.
The PLL compensation delay is 0 in this mode.
Excerpt of <project>.pt_timing.rpt:
Non-registered HSIO GPIO Configuration:
========================================

+---------------+----------+-------------+----------+----------+
| Instance Name | Pin Name |  Parameter  | Max (ns) | Min (ns) |
+---------------+----------+-------------+----------+----------+
|       i       |    i     |   GPIO_IN   |  0.828   |  0.552   |
|       o       |    o     |   GPIO_OUT  |  2.205   |  1.470   |
+---------------+----------+-------------+----------+----------+
The <project>.pt.sdc template is:
# Clock Latency Constraints
############################
# set_clock_latency -source -setup <board_max + 0.828> [get_ports {clk}]
# set_clock_latency -source -hold <board_min + 0.552> [get_ports {clk}]
There is no board delay in this example, therefore, the equations are:
<max calculation> = 0 + 0.828= 0.828
<min calculation> = 0 + 0.552 = 0.552
The resulting constraints are:
set_clock_latency -source -setup 0.828 [get_ports clk]
set_clock_latency -source -hold 0.552 [get_ports clk]