PLL Core Feedback Clock Latency

When using a PLL as a clock source you need to account for the any board delay, the GPIO input buffer delay (for the PLL's reference clock pin), and the PLL compensation delay.

Figure 1. Core Feedback Mode Delay

When the PLL is in core feedback mode, the compensation delay is equal to the clock network delay.

The SDC constraint formulas for the receive clock delay are:

set_clock_latency -source -setup <max calculation> <clock ports>
set_clock_latency -source -hold <min calculation> <clock ports>

The equations are:

<max calculation> = <max board constraint> + GPIO_INmax - <PLL compensation>

<min calculation> = <min board constraint> + GPIO_INmin - <PLL compensation>

The Efinity software v2023.2 and higher calculates the GPIO input buffer and PLL compensation delays and provides them in a template in the <project>.pt.sdc file. You still need to add any board delays if needed.

Setting PLL Core Feedback Clock Latency

In this example, the PLL clock output is called clk. This example assumes that the clock and data traces on the board are well matched; therefore, there is no external board delay.
Excerpt of <project>.pt_timing.rpt:
---------- 1. PLL Timing Report (begin) ----------
 
+--------+----------+-----------+-...-+------------------+------------------+
| PLL    | Resource | Reference | ... | PLL Compensation | PLL Compensation |
|Instance|          |   Clock   | ... | Delay Max (ns)   | Delay Min (ns)   |
+--------+----------+-----------+-...-+------------------+------------------+
|   pll  | PLL_TR0  | external  | ... |       4.310      |      2.155       |
+--------+----------+-----------+-...-+------------------+------------------+
 
+-------+-------------+-----------------------+
| Clock | Period (ns) | Phase Shift (degrees) |
+-------+-------------+-----------------------+
|  clk  |   10.0000   |           0           |
+-------+-------------+-----------------------+

Non-registered GPIO Configuration:
===================================
 
+---------------+----------+-----------+----------+----------+
| Instance Name | Pin Name | Parameter | Max (ns) | Min (ns) |
+---------------+----------+-----------+----------+----------+
|       i       |    i     |  GPIO_IN  |  1.396   |  0.698   |
|     refclk    |  refclk  |  GPIO_IN  |  1.476   |  0.738   |
|       o       |    o     |  GPIO_OUT |  3.829   |  1.915   |
+---------------+----------+-----------+----------+----------+
The <project>.pt.sdc template is:
# Clock Latency Constraints
############################
# set_clock_latency -source -setup <board_max -2.834> [get_ports {clk}]
# set_clock_latency -source -hold <board_min -1.457> [get_ports {clk}]
The equations are:
<max calculation> = 0 - 2.834 = -2.834
<min calculation> = 0 - 1.457 = -1.457
The numbers are negative because the PLL compensation is so much larger than the input delay.
The resulting constraints are:
set_clock_latency -source -setup -2.834 [get_ports clk]
set_clock_latency -source -hold -1.457 [get_ports clk]