PLL Cascading Clock Latency

When using cascaded PLLs as a clock source you need to account for the any board delay, the GPIO input buffer delay (for the PLL's reference clock pin), and the PLL compensation delay.

Note: You should cascade a maximum of 1 PLL, that is, the source PLL and the cascaded one.

Figure 1. PLL Cascade Delay

The SDC constraint formulas for the receive clock delay are:

set_clock_latency -source -setup <max calculation> <clock ports>
set_clock_latency -source -hold <min calculation> <clock ports>

The equations for the source PLL are:

<max calculation> = <max board constraint> - <source PLL clock latency>

<min calculation> = <min board constraint> - <source PLL clock latency>

The equations for the cascaded PLL are:

<max calculation> = <source PLL clock latency>_max + <cascaded PLL clock latency>_max

<min calculation> = <source PLL clock latency>_min + <cascaded PLL clock latency>_min

The Efinity software v2023.2 and higher calculates the GPIO input buffer and PLL compensation delays and provides them in a template in the <project>.pt.sdc file. You still need to add any board delays (if needed).

For the cascaded PLL, the software includes the clock network delay in the PLL compensation delay value.

The following example shows how to calculate the delays and set the constraints.

PLL Cascading Clock Latency

In this example, the PLL clock output is called clk. This example assumes that the clock and data traces on the board are well matched; therefore, there is no external board delay.

Excerpt of <project>.pt_timing.rpt:

---------- 1. PLL Timing Report (begin) ----------
 
+--------------+----------+-----------------+-...-+---------------------------------+---------------------------------+
| PLL Instance | Resource | Reference Clock | ... | PLL Compensation Delay Max (ns) | PLL Compensation Delay Min (ns) |
+--------------+----------+-----------------+-...-+---------------------------------+---------------------------------+
|   src_pll    | PLL_BL0  |     external    | ... |              2.346              |              1.519              |
|   casc_pll   | PLL_BL1  |       core      | ... |              2.341              |              1.516              |
+--------------+----------+-----------------+-...-+---------------------------------+---------------------------------+
 
+--------------+-------------+----------------------------+-----------------------+----------+
|    Clock     | Period (ns) | Enable Dynamic Phase Shift | Phase Shift (degrees) | Inverted |
+--------------+-------------+----------------------------+-----------------------+----------+
| src_pll_clk  |   10.0000   |           False            |          0.0          |  false   |
| casc_pll_clk |   10.0000   |           False            |          0.0          |  false   |
+--------------+-------------+----------------------------+-----------------------+----------+
 
---------- PLL Timing Report (end) ----------
 
---------- 2. GPIO Timing Report (begin) ----------
 
Non-registered GPIO Configuration:
===================================
 
+---------------+----------+-----------+----------+----------+
| Instance Name | Pin Name | Parameter | Max (ns) | Min (ns) |
+---------------+----------+-----------+----------+----------+
|     refclk    |  refclk  |  GPIO_IN  |  0.828   |  0.552   |
+---------------+----------+-----------+----------+----------+

The <project>.pt.sdc template is:

# Clock Latency Constraints
############################
# set_clock_latency -source -setup <board_max -1.517> [get_ports {src_pll_clk}]
# set_clock_latency -source -hold <board_min -0.967> [get_ports {src_pll_clk}]
# set_clock_latency -source -setup <board_max + 0.004> [get_ports {casc_pll_clk}]
# set_clock_latency -source -hold <board_min + 0.003> [get_ports {casc_pll_clk}]

The equations for the source PLL are:

<max calculation> = 0 - 1.517 = -1.517

<min calculation> = 0 - 0.967 = -0.967

The equations for the cascaded PLL are:

<max calculation> = 0 - 1.517 + 0.004 = -1.513

<min calculation> = 0 - 0.967 + 0.003 = -0.964

The numbers are negative because the PLL compensation is so much larger than the input delay.

The resulting constraints are:

set_clock_latency -source -setup - 1.517 [get_ports {src_pll_clk}]
set_clock_latency -source -hold - 0.967 [get_ports {src_pll_clk}]
set_clock_latency -source -setup - 1.513 [get_ports {casc_pll_clk}]
set_clock_latency -source -hold - 0.964 [get_ports {casc_pll_clk}]