Tri-State Buffers

Typically, you infer a tri-state buffer in your RTL code. For example:

module tri_state_buf_original (a);
    inout a;
    wire b;
    wire oe;
    assign a = (oe ? b : 1'bZ);
endmodule

In the Efinity® software, however, tri-state buffers are implemented as GPIO blocks in the Interface Designer. The following figure shows a tri-state buffer model in the Efinity® software. The Interface Designer promotes all of the internal signals of tri-state buffer to input and output ports of the RTL design (a_ena, a_in, and a_out).

To target Trion®, Topaz, and Titanium FPGAs, you map the inout port to three internal nodes (a_ena, a_in, and a_out), export all signals to the top-level module, and then assign the ports to GPIO. The following Verilog HDL code creates the tri-state buffer:

module tri_state_buf (a_in, a_out, a_ena, 
          internal_tri_state_buf_in, 
          internal_tri_state_buf_out, 
          internal_tri_state_buf_ena);

// Split the initial inout port a to three wrapper ports of tri-state buffer
input a_in;
output a_out;
output a_ena;

// Act as the internal tri state buffer signals.
output internal_tri_state_buf_out;
input internal_tri_state_buf_in;
input internal_tri_state_buf_ena;

// Modification from traditional way of inferring

assign internal_tri_state_buf_out = a_in;
assign a_out = internal_tri_state_buf_in;
assign a_ena = internal_tri_state_buf_ena; 

endmodule