RAM

Efinix® FPGAs have embedded RAM blocks that support simple dual-port memory and true dual-port memory. The read and write ports are registered. Asynchronous memory reads (e.g. in asynchronous FIFO or buffer implementation) can be bit-blasted into logic but may cause high device resource utilization. If you do not use the write port, the primitive acts as a ROM.
  • Trion FPGAs—During synthesis, the memory is mapped to EFX_RAM_5K (simple dual port) or EFX_DPRAM_5K (true dual port) primitives.
  • Titanium FPGAs—During synthesis, the memory is mapped to EFX_RAM10 (simple dual port) or EFX_DPRAM10 (true dual port) primitives.

The following sections provide code example for inferring these memories.

Notice: Refer to the Quantum® Trion Primitives User Guide for detailed information on the EFX_RAM_5K and EFX_DPRAM_5K primitives.
Refer to the Quantum® Titanium Primitives User Guide for information on the EFX_RAM10 and EFX_DPRAM10 primitives.