Synthesis Pragmas

synthesis on, synthesis off

This attribute directs synthesis to compile or skip a section of the RTL

full_case

This attribute directs synthesis to interpret case statements as full_case (similar to the Synopsys full_case pragma). If you use a full_case pragma, synthesis assumes that the listed cases are the only possible conditions. All other input combinations are don’t care and, therefore, synthesis does not generate logic for them

In the following example, the full_case pragma directs synthesis to treat the condition sel = 2’b11 as don’t care. The net effect is that the logic used to implement this case statement is simpler.

always @(a or b or c or sel) // synthesis full_case
  case (sel)
    2'b00: y = a;
    2'b01: y = b;
    2'b10: y = c;
  endcase

parallel_case

This attribute directs synthesis to interpret case statements as parallel_case (similar to the Synopsys parallel_case pragma). If you use the parallel_case pragma, synthesis does not assume that the case conditions are mutually exclusive, that is, they can be true at the same time.

In the following example, if sel = 3’b111, all three of the conditions match, and a, b, and c are assigned to 1’b1.

always @(sel)                
   begin
      {a, b, c} = 3'b0;
      casez (sel)                // synthesis parallel_case 
         3'b1??: a = 1'b1;
         3'b?1?: b = 1'b1;
         3'b??1: c = 1'b1;
      endcase
   end