Flip-Flops

The Efinity® synthesis tool recognizes flip-flops (or registers) while processing the RTL. Flip-flops can have these control signals:

  • Rising or falling edge clocks
  • Asynchronous set/reset
  • Synchronous set/reset
  • Clock enable
Figure 1. EFX_FF Symbol
Table 1. EFX_FF Ports
Port Direction Description
D Input Input data.
CE Input Clock Enable.
CLK Input Clock.
SR Input Asynchronous/synchronous set/reset.
Q Output Output data.

Flip-flops with active-high synchronous resets and active-high clock enables are described as sequential processes in VHDL. 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity D_FF_VHDL is
  port (clk, rst, ce, d  : in std_logic; q : out std_logic );
end entity D_FF_VHDL;

architecture Behavioral of D_FF_VHDL is
begin
  process (clk) is
  begin
     if rising_edge(clk) then  
        if (rst='1') then   
           q <= '0';
        elsif (ce='1') then
           q <= d;
        end if;
     end if;
  end process;
end architecture Behavioral;

They are described with an always statement in Verilog HDL. 

module D_FF_VERILOG (d, ce, clk, reset, out);   
  input d;    
  input ce;   
  input clk;   
  input reset;   
  output out;   
  reg q;    

  always @(posedge clk) begin     
    if (reset) q <= 1’b0;
    else if (ce) q <= d;   
  end    
  assign out = q;  
endmodule