Using the DSP Block Effectively

Fracturing lets the synthesis tool optimize how it packs operations into the DSP block. The packing density is the percentage of DSP Blocks that are fully occupied with EFX_DSP24 and/or EFX_DSP12 primitives. Theoretically, two EFX_DSP24 primitives or four EFX_DSP12 primitives pack into one EFX_DSP48. In practice, there are some restrictions on how well they can pack: legality constraints and packing quality constraints.

Legality Constraints

Synthesis can only pack EFX_DSP24 and EFX_DSP12 primitives into the same EFX_DSP48 if they are the same except for the datapath inputs/outputs. Generally:

  • Clock, CE, RST, SHIFT_ENA, and OP inputs to the EFX_DSP24 and EFX_DSP12 to be packed together must be identical nets​. You can use VCC, GND, or disconnected for these ports, as long as they match​.
  • All DSP primitive Verilog HDL parameters must match, including registered ports (A_REG, B_REG, W_REG) and the mode.

If you are not happy with the DSP Block packing density, you need to modify your design to allow them to pack more effectively.

Quality Constraints

The software avoids packing random DSP Blocks together because it can have a negative impact on fMAX. Instead, it tries to pack DSP blocks that are logically related—for example, ones that share neighbouring blocks and input nets—resulting in the best clustering that fits on the FPGA comfortably.

Improving Packing Density

If you want better DSP Block packing, there are some things you can try:

  • Tweak the design such that more DSP blocks have identical control signals and mode settings, and are thus packable. For example, try to avoid letting synthesis infer unique clock enables for every EFX_DSP24 and/or EFX_DSP12 primitive.
  • Setting the synthesis options --dspinout-regs-packing, --dsp-output-regs-packing, and --dsp-mac-packing to 0 may improve packing density at a cost of increased flipflop and adder consumption. You set these options in the Project Editor > Synthesis tab.

You can also use these reports to help with debugging:

  • place.rpt—This report includes a DSP packing summary that shows the number of DSP Blocks that would be packable if synthesis ignored control signal and attribute-related legality constraints. This number helps you understand whether tweaking the design to improve the packing density is even feasible. In practice, you can get about 50% packing improvement by tweaking the design. The report also lists the control set and attributes for each DSP Block. To be packed, EFX_DSP24 and EFX_DSP12 primitives must have matching control sets and attributes. Look for DSP Blocks that do not share control sets or attributes with other blocks, and then look at dsp_control_sets.csv for more detailed information on how to potentially adjust them.
  • dsp_control_sets.csv—This file is a table in .csv format that lists every control signal and attribute for every DSP Block. You can use a spreadsheet application to review the data to identify EFX_DSP24 and EFX_DSP12 primitives that are inferred with unique settings that make packing illegal.