syn_preserve

This attribute applies to signals. When it is set to true, yes, or 1, synthesis keeps the signal through optimization, that is, synthesis does not minimize or remove the signal. This attribute can be helpful when you want to simulate or view a signal in the Debugger. Although the signal is kept, synthesis may still choose to implement downstream functions that depend on this signal independent of this preserved signal.

In the Efinity software v2022.2 and higher, the syn_preserve attribute is supported on a user hierarchy instance. The effect is equivalent to tagging all boundary signals of the instance with syn_preserve.

Verilog HDL:
(* syn_preserve = "true" *) wire x;
VHDL:
attribute syn_preserve: boolean;
attribute syn_preserve of x : signal is true;
Note: A signal with syn_preserve usually has it’s name preserved through synthesis flow. However, if the signal is connected directly to a top-level port, the name in the map.v netlist may be changed to that of the top-level port name.