mark_debug

You use this attribute to mark debug nets for auto debug probe insertion. When set to true or 1, the synthesis tool writes out the selected signal to a default file (<project dir>/outflow/debug_profile.mark_debug.json).

The mark_debug attribute behavior is controlled by enable-mark-debug:
  • 0—Write an empty mark_debug.json json file
  • 1—Synthesis writes the selected signal to the default json file

The attribute is supported in the Efinity software v2025.1 and higher.

Verilog HDL: 
(* mark_debug = "true" *) wire x;
VHDL:
attribute mark_debug: boolean;
attribute mark_debug of x : signal is true;