Revision History

Corrected default clock constraint for non-expandable clocks (0.001 not 0.01). (DOC-2708)

Added --suppress_info_msgs, --suppress_warning_msgs, and --msg_suppression_list place and route options. (DOC-2599)

Updated place-and-route options. (DOC-2438)

Added --enable_mark_debug synthesis option.

Corrected D input connection in Figure 1.

Added check_timing and report_cdc commands. (DOC-2168)

Described how to read SDC files into a top-level SDC file. (DOC-2168)

Added Tcl Console section describing the enhanced Tcl support in v2024.1. (DOC-1824, DOC-1881)

Added get_fanins and set_bus_syntax_mode. (DOC-1722)

Added new options for create_generated_clock constraint. (DOC-1768)

Updated Best Practices for Constraining Routing and added example flow. (DOC-1891)

Added note emphasizing that you can only constrain routing for Titanium FPGAs. (DOC-1801)

Added get_fanouts constraint.

Updated Clock Latency section; the Efinity software v2023.2 now provides a SDC template for set_clock_latency.

Added clock latency topic for PLL cascading.

Updated section on constraining I/O.

Added section of common mistakes.

Updated topic about the <project>.pt.sdc file.

Updated topic about the <project>.pt_timing.rpt file.

In SDC files, square brackets are supported in clock names without using the -name option.

Added information on multiple SDC file support, including how the software handles multiple constraints for the same clock.

Added new examples for Clock Latency.

Added explanation for virtual clocks.

Added more detail and examples for constrainting unsynchronized inputs and outputs.

Added SDC examples.

Updated Best Practices for Constraining Routing to reflect syn_keep synthesis option.

Interpreting Timing Results topic updated for new report format.

Explained how to use clock names with square brackets in the name.

set_false_path, set_min_delay, and set_max_delay support clock domain, I/O and registers as the start and end point; they also support the -through option. (DOC-995)

Added section on constraining routing manually.

Added more details on synchronous input and output delays.

Added section on constraining logic.

Updated description for set_false_path constraint. Removed limitation that one end point much be a clock. (DOC-875)

Added set_clock_latency SDC constraint.

Updated the place-and-route options. (DOC-889)

Added -reference_pin flag to set_input_delay and set_output_delay. (DOC-488)

Added new synthesis options.

Added recommendation for closing timing for DSP Blocks.

Updated section on place-and-route options.

Restructured document and added more examples.

Added the efx_run_pnr_sweep.bat helper script.