The software may issue the following messages during timing analysis.
CannotDeriveGeneratedClockFromSpecifiedSourcePin (True)
| Message |
Error in generated clock {} : cannot derive master clock from the specified source pin |
| Decsription |
The Timer cannot find a generated clock from the specified source pin. Check your SDC constraints. |
CannotFindSpecifiedMasterClock (Warning)
| Message |
Clock {} is specified as the master clock for generated clock {} but it is not present in the fanin of the clock target. The fanin contains the following clocks: {} |
| Decsription |
The Timer cannot find specified master clock from timing netlist. Check your SDC constraints. |
CannotTraceBackToMasterClock (Warning)
| Message |
Could not trace back to master clock from target pin {}. Will assume zero latency on derived clock {} |
| Decsription |
Timer cannot trace back to master clock from target pin. |
ClockPeriodIsTooSmall (Warning)
| Message |
The clock period of {} is too small. Set to minimum clock period (1ps) |
| Decsription |
The minimum clock period for the Timer is 1 ps. Increase the clock period. |
CombinationalLoopDetected (Warning)
| Message |
Timer cuts a combinational loop at the {} |
| Decsription |
The software detected a combinational loop in the timing netlist. The Timer is cutting the edge an arbitrary point. |
IgnoreThruClockPinInException (Warning)
| Message |
When specifying exceptions, the -through cannot contain clocks. Ignoring the -through clock spec for this exception |
| Decsription |
When specifying exceptions with SDC constraints, the -through option cannot contain clocks. Ignoring the -through clock specification for this exception. Please check your SDC constraints. |
MissingNetInQDelay (Warning)
| Message |
Missing net on cell: {} port: {} in precomputed delay |
| Decsription |
Missing net in precomputed delay. |