Revision History

Updated for Efinity software v2025.2.

Documented new Package Planner features.

Described Python-JTAG co-debug feature.

IP Manager has a new feature for out of context (OOC) flows.

Added information about configuring external text editors to Setting General Tool Preferences. (DOC-2692)

Added note about GUI mode option for Aldec Active HDL simulation. (DOC-2694)

Added note about padding in combined bitstream images in Combine Bitstreams and Other Files.

Added messages that the software may issue during compilation. (DOC-2611)

Removed topics on installing USB drivers. Refer to the Efinity Software Installation User Guide instead.

Updated memory recommendations for 2025.2 release. (DOC-2703)

Updated default project file location. (DOC-2744)

Added limitation for iVerilog simulator: cannot simulated encrypted code (IP) or SystemVerilog. (DOC-2636)

Transceiver Debugger cannot determine the PCIe link width and speed when the PCIe link is in the polling compliance state (this behavior is expected). (DOC-2738)

Updated instructions for using the BRAM Initial Content Updater example files. (DOC-2717)

Added Module Resource Usage Distribution Estimates table description to the .place.rpt project file appendix. (DOC-2705)

Updated content in Concurrent Debugging to reflect new procedures. (DOC-2731)

IP Manager generates additional files for out-of-context (OOC) synthesis. (DOC-2761)

Updated device support.

Updated Interface Primitive Simulation Models table.

Updated device support.

Updated device support.

Updated for Efinity software v2025.1.

Removed "Appendix: Connecting Programming Hardware." Refer to the configuration application notes for this information.

Added topic describing Setting User and Project Directories. (DOC-2465)

Removed Auto-Load Place-and-Route topic. This feature is no longer needed with v2025.1. (DOC-2284)

Updated machine memory requirements. (DOC-2286)

Added "Using Mark Debug" subtopic in "Debugging Overview". (DOC-2344)

Updated description of where you add the .isf to your project, see Design Tab. (DOC-2472)

Added instructions for simulating with the Aldec Active HDL or Riviera-PRO simulators. (DOC-2463)

Added description of the Transceiver Debugger's BIST function. (DOC-2469)

You can now launch the Efinity RISC-V Embedded Software IDE from the Efinity GUI. (DOC-2430)

Added topic on combining multiple image files at the command line. (DOC-2231)

Generate Efinity Constraints Files button renamed as Generate Interface Output Files. (DOC-2296)

Updated device support table for Tz100G400, Tz170G400, Ti180J484D1, and Ti135N484.

Updated for patch 2024.2.294.3.14.

Added support for Ti180 J484D1 packages.

Added topic on resolving IP Manager issues. (DOC-2345)

Updated for patch 2024.2.294.2.12.

Added bitstream support for Tz200 and Tz325 FPGAs in C529 packages.

Added bitstream support for Ti165 and Ti240 FPGAs in C529 packages.

The HyperRam Controller IP Core no longer supports Trion FPGAs. (DOC-2312)

Updated instructions for installing Linux USB drivers. (DOC-2279)

Updated for patch 2024.2.294.1.19.

Added C529 package for Tz200 and Tz325.

Added bitstream support for Ti375 in N484 package and Tz110 and Tz170 in J361 and J484 packages.

Added new features in 2024.2.

Updated device support.

Project Editor > Design tab > Top Module/Entity cannot be left empty. (DOC-2137)

Corrected link to latest Microsoft Visual C++ Redistributable downloads. (DOC-2045)

An EFX_FF primitive cannot be placed in a Trion ELF tile.

Described .f files for referencing RTL source code. (DOC-2072)

Updated screen shots for unified design options. (DOC-2184)

Added Linux requiremens fro Java. (DOC-2056)

Added new # Trigger option for Debugger Logic Analyzer. (DOC-1886)

Double-clicking a file in the Project or Result pane opens it in the default or user editor. (DOC-2146)

Added topic about encrypting and/or signing bitstreams at the command line.

Added topic on Packaging Design Files.

Red Hat support is v8.0 and higher. Removed support for v7.4. (DOC-1648)

The Console supports color output and dark mode. (DOC-1762)

Added the sta_tclsh flow option to open the Tcl Console frorm the command line. (DOC-1881)

Added chapter on the Efinity Transceiver Debugger. (DOC-1941)

The software has separate .bit files for JTAG Bridge (New) and JTAG Bridge (Legacy), and they are not compatible with each other. The .bit files do not require an external clock. (DOC-1789)

Pinout is final for F100 package for the Ti35 and Ti60 FPGAs.

Q3 timing model is final for the Ti90, Ti120, and Ti180 FPGAs in the J484 package.

Added F256 package for the T35 FPGAs.

Added JTAG device IDs for Ti135, Ti200, and Ti375.

Added note explaining that you should make a backup of your existing project before opening it in a newer software version because the project files are not backwards compatible. (DOC-1632)

Added note about Windows %PATH% variable to Hardware and Software Requirements. (DOC-1687)

Updated device support and new in v2023.2.

Updated machine memory requirements.

For Windows, a 64-bit operating system is required. 32-bit systems are not supported.

Added explanation about the input and output numbers listed in the Core Resoures section of the Result pane and in the <project>.place.rpt file.

You can open multiple Debugger windows by clicking the Debugger icon multiple times.

Added information on how to reference Trion and Titanium VHDL primitive libraries.

Added bitstream support for G400 packages.

Added note to use only ASCII characters. (DOC-1522)

Added G400 package support. (DOC-1393)

Added section about the Netlist Viewer tool.

Added section about the BRAM Initial Content Updater.

Updated description for Preferences dialog box.

Added topic on how to preserver place-and-route for a portion of your design.

Added additional information on design migration.

Added appendix describing all tools included with the Efinity software.

Added section on constraining routing manually.

EFX_COMB4 not available in Trion FPGAs. (DOC-1074)

Added description of Debugger Options menu. (DOC-1029)

Added topics on how to constrain routing (beta).

Updated PFGA support for Efinity patch 2022.1.226.1.9.

Updated the available options for theProject Editor > Place and Route tab. (DOC-889)

Clarified the instructions for instantiating debug cores. (DOC-883)

Clarified that when using internal reconfiguration you must use Programmer > Combine Multiple Image Files > Image Type > Internal Flash Image option. (DOC-874)

Added topic on verifying configuration with the Programmer.

When editing the bitstream header, do not remove any auto-generated data or the Programmer may not recognize the bitstream.

Removed support for C232HM-DDHSL-0 cable. (DOC-860)

Added a topic on the concurrent debug feature.

Updated supported IP cores.

Updated Installing USB Drivers topics.

Updated supported IP cores.

Added topic on combining a bitstream and other data into a single file for programming.

Re-organized topics about working with bitstreams.

Moved topics on installing USB drivers and connecting programming hardware to the appendix.

The minimum operating frequency of the debug cores is 2 times the JTAG TCK frequency. (DOC-754)

Added CORDIC core to the list of supported IP (included with Efinity patch v2021.2.323.2.18).

Added Efinity Hardware Server documentation. (DOC-598)

Added support for FTDI FT4232H Mini Module. (DOC-597)

Added the JTAG USERCODE option to the Project-Based Programming Options topic.

Added instructions on using the Titanium bitstream security features.

Added instructions for using the Efinity SVF Player.

Described how to export a bitstream to serial vector format (.svf).

Added instructions for importing IP cores. (DOC-584)

Added topic on flash programming modes.

Added topic on the Titanium configuration status registers. (DOC-487)

Added note that FTDI Chip FT2232H Mini Module supports 3.3 V I/O voltage only. (DOC-495)

Added description of command to convert bitstream files from .hex to .bin to Exporting to Raw Binary Format topic. (DOC-527)

Added support for Titanium family.

Corrected JTAG chain file code example. (DOC-368)

Explained how to resize the Project, Netlist, and Result panes.

Described the context-sensitive menus in the Project, Netlist, and Result panes.

Corrected JTAG Mini Module pin names for T4, T8, T13, T20BGA256, and T20BGA169 connection setup.

Clarified Undefined clock domain signals in the Debug Wizard.

Added table of files shown in the Result pane. (DOC-277)

Updated instructions on installing Windows USB drivers.

Added FTDI cable and module connection for T20BGA400.

Added JTAG device IDs for T20BGA324 and T20BGA400.

Removed the FTDI2232 from About USB Drivers topic making the description applicable to other FTDI chips.

Corrected the command for using --pgm_opts with the command-line programmer.

Windows 7, Red Hat v6, and CentOS v6 no longer supported.

Removed the chapters on SDC constraints and Tcl commands. This content is now in the Efinity Timing Closure User Guide.

Added a topic on Efinity synthesis.

Added a topic on project migration.

Updated Programmer content to reflect new GUI and features.

Consolidated and updated content on installing USB drivers for boards, C232HM-DDHSL-0 cable and FTDI FT2232H module.

Added support for FTDI FT2232H module for JTAG programming.

Added a topic on the various ways to view messages and logs.

Added topic on the Interface Designer/s Resource View.

Added a topic on using an API for scripting an interface design.

Added topic on Interface Scripting File (.isf).

Added chapter on using the Debugger.

Added explanation that 2 unassigned pairs of LVDS pins should be located between and GPIO and LVDS pins in the same bank.

Added information on enhanced Resource Assigner.

Added information on JTAG programming.

Added command-line instructions for using the Windows efx_run.bat file.

Added information on new project manager capabilities.

Updated set_false_path usage.

Added more information on simulation and waveform viewing.

Added Python 3 to the software requirements list as an option. For Windows, if you do not have a full version of Python, the .py extension may not be correctly associated with Python.

Removed Python requirement; as of this release, Python is included with the software.

Added the requirement that Windows users install the Microsoft Visual C++ 2015 x64 runtime library.

Updated for v2018.0 release.

Added “Constraining Logic and Assigning Pins” topic, which replaces section on fine-tuning your design.

Updated information on device configuration.

Updated for v2017.0 release.

Described new Floorplan Editor tools.

Updated SDC constraint information.

Updated for v2016.0 release.

Documented the Timing Browser.

Documented the Tcl Command Console and available Tcl commands.

Updated SDC constraint information.