Appendix: Efinity Tools
This topic provides a list of tools included with the Efinity software.
| Tool | Description | Read More |
|---|---|---|
| Bitstream Security Key Generator | Simplifies the process of creating encryption keys and generating RSA certificates (for Titanium FPGAs only). | Using the Efinity Bitstream Security Key Generator |
| BRAM Initial Content Updater | Lets you quickly update the initial memory saved in the FPGA's BRAM without performing a full compile. | About the BRAM Initial Content Updater |
| Code Editor | Basic editor for viewing code or report files. You should use your own editor for real coding work. | |
| Debugger | Use to probe signals in your FPGA design via the JTAG interface. | Debugging |
| Debug Wizard | Provides an automated flow for adding a logic analyzer core to your design. | Debug Wizard |
| Floorplan Editor | Provides a graphical view of the logic and routing in your design. | |
| Interface Designer | Used to build the peripheral portion of your design such as PLLs, GPIO, MIPI, DDR, etc. | About the Interface Designer |
| IP Packager | Use this tool to "package" design files for re-use in the IP Manager. | Packaging Design Files |
| IP Manager | Interactive wizard that helps you customize and generate Efinix IP cores. | Using the IP Manager |
| JTAG SVF Player | JTAG SVF player that sends JTAG commands to an Efinix FPGA. | Using the Efinity SVF Player |
| Log Message | Tool to sort and browse through all of the messages resulting from the compilation flow. | Viewing Messages and Logs |
| Message Browser | Shows synthesis-specific messages that result when you elaborate the netlist. | Viewing Messages and Logs |
| Netlist Viewer | Displays and analyzes your design's netlist, including all components and their connections (nodes and nets). | Netlist Viewer (Beta) |
| Package Planner | Provides a visual representation of the FPGA package pins. | Editing and Viewing the Package Pinout |
| Programmer | Select bitstream images and program the FPGA directly or the flash device on a board. | About the Programmer GUI |
| Efinity RISC-V Embedded Software IDE | Develop and debug software for the Sapphire SoC suite of RISC-V processors. | Efinity RISC-V Embedded Software IDE |
| Tcl Command Console | Enter Tcl commands to analyze and explore timing. | |
| Timing Browser | Helps you explore your design’s critical paths and the cells of those paths. | |
| Transceiver Debugger | Lets you test and display the signal quality of the FPGA's transceiver signals. | Debugging Transceivers |