Efinix, Inc.
  • Efinity User Guides
  • Efinity Software User Guide
    • Setting Up
      • Efinity Quick Start
      • Setting General Tool Preferences
      • Setting User and Project Directories
      • Efinity Main Window
    • Managing Projects
      • Project Editor
      • Project Tab
      • Referencing RTL Source Files
      • Using VHDL Libraries
      • Packaging Design Files
      • Migrating a Project to another FPGA
    • Running the Tool Flow
      • Run the Flow with the Dashboard Controls
      • Run the Flow from the Command Line
      • About Efinity Synthesis
      • Netlist Tab
      • Netlist Viewer (Beta)
        • Opening the Netlist Viewer
        • Zooming
        • Highlighting and Marking
        • Viewing the Netlist Hierarchy
        • Finding Elements
        • Viewing a User-Defined Element
        • Viewing an Element's Connectivity
        • Viewing the Action History
      • Viewing Messages and Logs
      • Result Tab
      • Viewing Place-and-Route Results
      • Efinity RISC-V Embedded Software IDE
    • Using the IP Manager
      • Supported IP Cores by Family
      • Using the IP Configuration Wizard
      • Generated Files
      • Instantiating IP in Your Project
      • Managing IP in Your Project
      • IP Settings File
      • Getting Updated IP
      • Resolving IP Manager Issues
    • Constraining Logic and Assigning Pins
      • About the Interface Designer
      • Get Oriented
      • Using the Resource Assigner
      • Resource View
      • Importing and Exporting Assignments
        • Interface Scripting File
        • .csv File for GPIO Blocks
      • Scripting an Interface Design
      • Editing and Viewing the Package Pinout
        • Selecting a Pin
        • Browsing for Pins
        • Drag-and-Drop Assignments
        • Excluding Pins and Banks
      • Constraining Logic and Routing Manually (Beta)
        • Tiles
        • Working with Primitives
        • Enabling Manual Assignments
        • Assignment Rules
        • Creating a Location Assignment File
        • Constraining Routing Manually (Beta)
          • Routing Constraint Flow
          • Generate .rcf Template
          • Creating a Routing Constraint File
          • Enabling Routing Constraints
          • Best Practices for Constraining Routing
          • Example Flow
    • Analyzing Timing
    • Simulating
      • Simulation Models
      • Changing the Default Testbench Names
      • Simulate with the iVerilog Simulator
        • View Waveforms
      • Simulate with the ModelSim Simulator
      • Simulate with the NCSim Simulator
      • Simulate with the Aldec Active HDL or Riviera-PRO Simulator
    • Debugging
      • Profile Editor Perspective
        • Virtual I/O Debug Core
        • Logic Analyzer Debug Core
      • Debug Wizard
      • Debug Perspective
        • Logic Analyzer Perspective
          • Understanding Capture Control
        • Virtual I/O Perspective
      • Debugger Options
      • Using the mark_debug Synthesis Attribute
      • Concurrent Debugging
      • Resource Usage
      • Disable the Debug Core
    • Debugging Transceivers
      • Launching the Transceiver Debugger
      • Using the Transceiver Debugger
      • Debugging with BIST
      • Sending Commands
      • Interpreting the Results
    • Configuring an FPGA
      • FPGA Configuration Modes
      • Flash Programming Modes
      • About the Programmer GUI
        • Edit the SPI Active Clock
      • Generate a Bitstream (Programming) File
      • About the BRAM Initial Content Updater
        • Updating the BRAM Initial Content
        • Using the Example Files
        • Use Another Board
        • Run the BRAM Initial Content Updater from the Command Line
      • Working with Bitstreams
        • Edit the Bitstream Header
        • Bitstream Compression
        • Export to Raw Binary Format
        • Export to .svf Format
        • Convert to Intel Hex Format at the Command Line
        • Combine Bitstreams and Other Files
        • Combine Bitstreams at the Command Line
      • SPI Programming
        • Program a Single Image
        • Program Multiple Images (CBSEL)
        • Program Multiple Images (Internal Reconfiguration)
        • Program Multiple Images (Bitstream and Data)
        • Program a Daisy Chain
      • JTAG Programming
        • Trion Family JTAG Device IDs
        • Titanium Family JTAG Device IDs
        • Topaz Family JTAG Device IDs
        • Program a Single Image
        • Program Using a JTAG Chain
        • Program using a JTAG Bridge
        • JTAG Programming with FTDI Chip Hardware
        • FTDI Programming at the Command Line
        • Identifying FTDI URLs
      • Programmer Messages
      • Using the Command-Line Programmer
      • Project-Based Programming Options
      • Configuration Status Register
      • Verifying Configuration with the Programmer
      • Securing Titanium Bitstreams
        • Using the Efinity Bitstream Security Key Generator
        • Blowing Fuses with the SVF Player
        • Enabling Security for Your Project
        • JTAG Command Support with Security Enabled
        • Encrypt or Sign Bitstreams from the Command Line
        • Workflow for Using Security Features
        • Verifying Security Settings
    • Working with JTAG .svf Files
      • Using the Efinity SVF Player
      • Export JTAG Operations at the Command Line
    • Working with Remote Hardware
  • Efinity Installation User Guide
    • Overview
    • Hardware and Software Requirements
    • Third-Party Simulator Support
    • Installing the Efinity Software
    • Installing Patches
    • Setting User and Project Directories
    • Proxy Settings
    • Efinity Quick Start
    • Appendix: Installing USB Drivers
      • Installing the Linux USB Driver
      • Installing the Windows USB Driver
    • Where to Learn More
    • Troubleshooting
    • Revision History
  • Efinity Synthesis User Guide
    • Introduction
      • SystemVerilog and Verilog HDL Support
      • VHDL Support
      • Specifying Language Support
      • Synthesis Project Settings
      • Netlist Tab
    • Design Guidelines
      • DSP
        • Inferring DSP
          • Inferring Wide Multipliers
          • Floating-Point Operation
        • Using the DSP Block Effectively
        • Timing Considerations
      • Flip-Flops
        • Flip-Flop Reporting
        • Flip-Flop Guidelines
      • Latches
      • RAM
        • Inferring RAM
        • Estimating Block RAM Resources
      • Inferring Shift Registers
      • Tri-State Buffers
    • Synthesis Options
      • Example: --infer-clk-enable
      • Example: --create-onehot-fsms
      • Example: --allow-const-ram-index
      • Example: --msg_suppression_list
      • Retiming
      • Sequential Optimization
    • Synthesis Pragmas
    • Synthesis Attributes
      • async_reg
      • mark_debug
      • skip_ram_init
      • syn_extract_enable
      • syn_keep
      • syn_peri_port
      • syn_preserve
      • syn_ramdecomp
      • syn_ramstyle
      • syn_romstyle
      • syn_srlstyle
      • syn_use_dsp
      • translate_on, translate_off
    • Out-of-Context Synthesis
      • Export Project Files as OOC Archive
      • Generate OOC Files with IP Manager
      • Import OOC Files
    • Using VHDL Libraries
      • Referencing Efinix VHDL Libraries
    • VHDL 2008 Support
      • Relational Operators (9.2.1)
      • Condition Operator (9.2.9)
      • Vector Aggregates (9.3.3)
      • Conditional and Sequential Statements (10.5.3, 10.5.4)
      • Case Statements with Don't Care (10.9)
      • Sensitivity List (11.3)
      • Generate Statements (11.8)
      • Expressions in Port Maps (11.8)
      • Enhanced String Literals (15.8)
      • Block Comments (15.9)
      • Fixed-Point Handling (16.10)
      • Minimum() and Maximum() Functions (16.3)
    • VHDL 2019 Support
      • VHDL 2019 Interface Usage
      • VHDL 2019 Example
    • SystemVerilog Support
      • Hierarchical Names Support
    • Warning and Error Messages
      • Synthesis Messages
      • Post-Synthesis Check Messages
    • Where to Learn More
    • Revision History
  • Efinity Timing Closure User Guide
    • Introduction
      • About Constraints
      • Tools for Exploring Timing
    • SDC File Overview
      • About SDC Files
      • Create an Empty SDC File
      • Add an SDC File to Your Project
      • Using Multiple SDC Files
      • Efinity Files You Use to Create Constraints
    • Constraining Clocks
      • Defining Clocks
        • Using the create_clock Constraint
        • Using the create_generated_clock Constraint
        • Virtual Clocks
      • Clock Latency
        • GPIO Clock Latency
        • PLL Local Feedback Clock Latency
        • PLL Core Feedback Clock Latency
        • PLL External Feedback Clock Latency
        • PLL Cascading Clock Latency
      • Clock Relationships
        • Setting Constraints for Unrelated Clocks
        • Using the set_clock_groups Constraint
        • Using the set_false_path Constraint
        • Clock Synchronizers
        • Metastable Synchronizer Circuit
      • How to Set Clock Uncertainty
    • Constraining I/O
      • Constraining Synchronous Inputs and Outputs
      • Constraining Unsynchronized Inputs and Outputs
        • Input Receive Clock Delay
        • Output Receive Clock Delay
        • Input Forward Clock Delay (GPIO clkout)
        • Output Forward Clock Delay (GPIO clkout)
        • Input Forward Clock Delay (GPIO output)
        • Output Forward Clock Delay (GPIO output)
    • Timing Exceptions
      • Example: Clock-to-Clock Path with Control
      • Understanding False Paths
      • Understanding Min and Max Delays
      • Understanding Multicycle Constraints
        • Shifted Capture Window
        • Shifted and Widened Window
        • Constraints between Fast and Slow Clocks
    • SDC Warnings
    • Common Mistakes
    • SDC Tips and Tricks
      • SDC Syntax
      • Wildcard Commands
      • Regular Expressions
      • Inverted Clocks
      • Square Brackets in Clock Names
    • SDC Constraints (Alphabetical)
      • create_clock Constraint
      • create_generated_clock Constraint
      • get_fanouts Constraint
      • get_fanins Constraint
      • set_bus_skew Command
      • set_bus_syntax_mode Command
      • set_clock_groups Constraint
      • set_clock_latency Constraint
      • set_clock_uncertainty Constraint
      • set_false_path Constraint
      • set_input_delay and set_output_delay Constraints
      • set_max_delay and set_min_delay Constraints
      • set_multicycle_path Constraint
      • -through Option
    • Object Specifiers
    • SDC Examples
      • Example: Dynamic Multiplexers and create_clock -add
      • Example: FPGA Forwarded Clock
      • Example: Generated Clock with Clock Multiplexer
      • Example: Soft SERDES
      • Example: Disable Impossible Paths
    • Interpreting Timing Results
      • Clock Frequency Summary
      • Clock Relationship Summary
      • Critical Paths
    • Constraining Logic and Routing Manually (Beta)
      • Tiles
      • Working with Primitives
      • Enabling Manual Assignments
      • Assignment Rules
      • Creating a Location Assignment File
      • Constraining Routing Manually (Beta)
        • Routing Constraint Flow
        • Generate .rcf Template
        • Creating a Routing Constraint File
        • Enabling Routing Constraints
        • Best Practices for Constraining Routing
        • Example Flow
    • Methods for Closing Timing
      • Synthesis Options
        • Handling High Fanouts
      • Place-and-Route Options
        • Beneficial Skew
        • Sweeping Script
        • Optimization Sweeping
        • Seed Sweeping
        • Message Suppression List
      • Timing Considerations
    • Tcl Console
      • General Commands
        • delete_timing_results Command
        • get_available_timing_model Command
        • get_timing_model Command
        • read_sdc Command
        • reset_timing Command
        • set_timing_model Command
        • write_sdc Command
      • Report Commands
        • check_timing Constraint
        • report_bus_skew Command
        • report_clocks Command
        • report_path Command
        • report_cdc Command
        • report_timing Command
        • report_timing_summary Command
      • Tcl List Functions (Alphabetical)
        • lappend
        • lassign
        • lindex
        • linsert
        • llength
        • foreach_in_collection
        • foreach
        • lrange
        • lreplace
        • lreverse
        • lsearch
        • lsort
      • Tcl Script Examples
        • Identify Pins with a Regular Expression
        • Create Clocks with Different Periods
        • Generate a Report with get_fanouts
        • Generate Report with a Subset of Clocks
        • Use Variable for Min/Max Delay Calculation
      • Perform Static Timing Analysis at the Command Line
    • Appendix
      • About the <project>.pt.sdc File
      • About the <project>.pt_timing.rpt File
      • SDC Constraint Messages
      • Timing Analysis Messages
    • Where to Learn More
    • Revision History
  • Efinity Python API
    • Introduction
      • About the API Functions
      • Blocks and Their Properties
      • Interface Scripting File
    • Working with Python
      • Code Blocks
      • Variables
      • Data Types
      • Displaying a Variable's Value
      • Functions
      • Handling Errors
    • Elements of a Python Script
    • How to Run a Script
    • Issuing Commands in the Python Console
    • Getting Help
    • Example Scripts
    • API Classes
    • API Functions by Category
      • Design Management Functions
      • Create Block Functions
      • Delete Block Functions
      • Get Block Functions
      • Block Property Functions
      • Bus Functions
      • Resource Functions
      • Package Pin Functions
      • Clock Functions
      • Device Settings
      • Preset Settings
      • PCIe Functions
      • Constraint and Report Functions
      • Design Check Functions
      • API Information Functions
      • IP Manager Functions
    • API Functions: Interface Designer
    • API Functions: IP Manager
    • Block Types and Device Settings
    • Clock Multiplexer Property Reference
    • DDR Property Reference
      • Trion DDR Properties
      • Titanium and Topaz DDR Properties
    • Ethernet SGMII Property Reference
    • Ethernet XGMII Property Reference
    • External Flash Controller Property Reference
    • GPIO Property Reference
      • GPIO Input Properties
      • GPIO Output and Output Enable Properties
      • GPIO Bus Properties
      • GPIO General Properties
    • HyperRAM Property Reference
    • I/O Bank Property Reference
    • JTAG Property Reference
    • LVDS Property Reference
    • MIPI Property Reference
    • MIPI D-PHY Property Reference
    • MIPI Lane Property Reference
    • OSC Property Reference
    • PCIe Property Reference
    • PLL Property Reference
    • PLL SSC Property Reference
    • PMA Direct Property Reference
    • Remote Update Property Reference
    • SEU Property Reference
    • SPI Flash Property Reference
    • SOC Property Reference
    • Exceptions
    • Where to Learn More
    • Revision History
  • Efinity Programmer User Guide
    • Introduction
    • Hardware and Software Requirements
    • Installing
      • Installing Patches
    • FPGA Configuration Modes
    • Flash Programming Modes
    • About the Programmer GUI
      • Working with Bitstreams
        • Edit the Bitstream Header
        • Bitstream Compression
        • Export to Raw Binary Format
        • Export to .svf Format
        • Convert to Intel Hex Format at the Command Line
        • Combine Bitstreams and Other Files
        • Combine Bitstreams at the Command Line
      • SPI Programming
        • Program a Single Image
        • Program Multiple Images (CBSEL)
        • Program Multiple Images (Internal Reconfiguration)
        • Program Multiple Images (Bitstream and Data)
        • Program a Daisy Chain
      • JTAG Programming
        • Trion Family JTAG Device IDs
        • Titanium Family JTAG Device IDs
        • Topaz Family JTAG Device IDs
        • Program a Single Image
        • Program Using a JTAG Chain
        • Program using a JTAG Bridge
        • JTAG Programming with FTDI Chip Hardware
        • FTDI Programming at the Command Line
        • Identifying FTDI URLs
      • Programmer Messages
      • Using the Command-Line Programmer
      • Configuration Status Register
    • Verifying Configuration with the Programmer
    • Verified Flash Devices
    • Working with Remote Hardware
    • Securing Titanium Bitstreams
      • Using the Efinity Bitstream Security Key Generator
      • Blowing Fuses with the SVF Player
      • Encrypt or Sign Bitstreams from the Command Line
      • Workflow for Using Security Features
      • Verifying Security Settings
      • JTAG Command Support with Security Enabled
    • Working with JTAG .svf Files
      • Using the Efinity SVF Player
      • Export JTAG Operations at the Command Line
    • Where to Learn More
    • Appendix: Installing USB Drivers
      • Installing the Windows USB Driver
    • Appendix: Program using a JTAG Bridge (Legacy)
    • Revision History
  • Efinity Command-Line User Guide
    • Introduction
      • Using Efinity Command-Line Scripts
      • Efinity Quick Start
    • Run the Flow from the Command Line
      • efx_run Script
      • --flow Option
      • Place and Route Multi-Run Script
      • Perform Static Timing Analysis at the Command Line
    • Simulating
      • Simulation Models
      • Changing the Default Testbench Names
      • Simulate with the iVerilog Simulator
        • View Waveforms
      • Simulate with the ModelSim Simulator
      • Simulate with the NCSim Simulator
      • Simulate with the Aldec Active HDL or Riviera-PRO Simulator
    • Configure FPGAs at the Command Line
      • Launch the Debugger from the Command Line
      • Using the Command-Line Programmer
      • FTDI Programming at the Command Line
      • Use the SVF Player at the Command Line
      • Identifying FTDI URLs
      • Run the BRAM Initial Content Updater from the Command Line
      • Using the Block RAM Resource Estimator
    • Manage Bitstream Files at the Command Line
      • Generate Bitstream Checksums at the Command Line
      • Convert to Intel Hex Format at the Command Line
      • Combine Bitstreams at the Command Line
      • Encrypt or Sign Bitstreams from the Command Line
      • Using the Efinity Database Export Utility (Beta)
      • Export JTAG Operations at the Command Line
    • Appendix: Additional Flow Options
      • Synthesis Options
      • Place and Route Options
      • Programming Options
    • Where to Learn More
    • Revision History

Efinity Source Files for Version Control

If you want to put your project under revision control, the files you need to store (in addition to your RTL) are:

  • <project>.xml
  • <project>.peri.xml
  • <project>.sdc
  • debug_profile.wizard.json
  • dbg_top.v
  • <module>.v
  • settings.json

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