set_clock_latency Constraint

set_clock_latency [-clock <names>] [-rise] [-fall] -source <latency> 
    [-setup] [-hold] <latency> <target clock, port, or pin>

The source latency represents the time it takes (in ns) for a clock signal to get from the source to the destination such as the delay from an oscillator to the FPGA's input pad. You can only set the clock source latency for clock and clock source pins. You musty specify a source. If do no specify -rise or -fall, the latency is applied to both clock edges.

  • -clock Specifies a list of clocks associated with the latency assigned to the specified clock source.
  • -rise Defines the latency for the rising clock edge.
  • -fall Defines the latency for the falling clock edge
  • -source Defines the specified <latency> as the source latency. This argument is required.
  • -setup Define the clock edge delay for setup analysis
  • -hold Define the clock edge delay for hold analysis
set_clock_latency -source -rise -0.5 [get_ports clk200]
set_clock_latency -source -fall -0.4 [get_ports clk200]
set_clock_latency -source -fall 0.1 {clk25~FF|Q} -clock {clk200 clk50}
set_clock_latency -source 0.7 [get_pins clk_50~FF|Q]