Object Specifiers

SDC constraints and Tcl commands support explicit object specifiers. Implicit naming is implied if you do not use an object specifier with the constraint command. If you do not use an object specifier the software executes the search on the objects in the following order: nets, pins, cells.

The name you provide to the object specifier is based on the post-mapped design name; refer to the generated post-mapped Verilog HDL netlist—autogenerated by the software at the end of synthesis—for these names.

Note: The pipe (|) character is the separator between the instance name and the referenced port name.

In the Efinity software v2024.1 and higher, the object specifiers return Efinity Tcl objects or collections (in earlier versions they returned strings). This functionality allows you to use the results with Tcl list functions to navigate a netlist or generate custom timing reports. (See Tcl List Functions (Alphabetical).)

  • all_clocks—Retrieves a collection Efinity Tcl objects representing all of the design's clocks.
  • all_inputs—Retrieves a collection of Efinity Tcl objects representing all of the design's input ports.
  • all_registers—Retrieves a collection of Efinity Tcl objects representing all of the design's register instances.
  • all_outputs—Retrieves a collection of Efinity Tcl objects representing all of the design's output ports.
  • get_cells [-regexp] [<filter>]—Retrieves Efinity Tcl objects that match the specified cell name or pattern.1
  • get_clocks [-regexp] [<filter>]—Retrieves Efinity Tcl objects that match the specified clock name or pattern. The tool looks first for the clock name, if it exists. Next, it checks the clock net name (includes virtual clocks).1
  • get_nets [-regexp] [<filter>]—Retrieves a collection of Efinity Tcl objects that matches the specified net name or pattern.1
  • get_pins [-regexp] [<filter>]—Retrieve a collection of Efinity Tcl objects that matches the specified pin name or pattern. The pin name format is <cell>|<port>. Escape square brackets for cell names; you do not need to escape square brackets for ports if the port has bit indexing.1
  • get_ports [-regexp] [<filter>]—Retrieve a collection of Efinity Tcl objects that matches the specified port name or pattern.1

Because these object specifiers return return Efinity Tcl objects, you can use them together in a nested format.

Example 1: Get a group of cells based on a pattern and the find the pins for the selected cells:
set pin_list [ get_pins [get_cells <pattern>]]
Example 2: Get a set of pins based on a pattern and then find the nets for those pins:
set net_list [get_nets [get_pins <pattern>]]
Example 3: Get a group of cells based on a pattern and then find the net connection based on the pins:
set nets_on_cell_pin [get_nets [get_pins [get_cells <pattern>]]]
Example 4: Get the nets for a group of ports:
set nets_on_ports [get_nets [get_ports out[*]]]
1 By default, you do not need to escape brackets. However, if you use the -regexp option, you must escape all brackets.