Revision History
| Date | Version | Description |
|---|---|---|
| December 2025 | 1.8 | Fix error in Table 1. (DOC-2810) Added Hot Plug Interface Signals and
Appendix F: Hot Plug Support.
(DOC-2831) |
| November 2025 | 1.7 | Added Link Initialization and Training. (DOC-2735) |
| June 2025 | 1.6 | Updated AXI read: TLP (2n and 2n>1, up to 32 Bytes, Unaligned Address). (DOC-2528) Updated AXI write: AXI Master Write Operation.
(DOC-2528) Added End-to-End Data Protection.
(DOC-2541). Updated Clock Sources. (DOC-2572) Updated Function-Level Reset Signals.
(DOC-2541) Updated note in Figure 1. (DOC-2541) |
| April 2025 | 1.5 | Fixed typos in AXI Master Read Operation. (DOC-2515) |
| April 2025 | 1.4 | Added Appendix E: Supported Chipsets.
(DOC-2207) Update Table 1. (DOC-2493) |
| February 2025 | 1.3 | Added note about incompatible clock tolerances for SRIS.
(DOC-2265) Added information on clock sources from PLLs.
(DOC-2265) Clarified supported SPI active configuration
details. (DOC-2265) |
| January 2025 | 1.2 | Updated Interrupt Sideband Signals. |
| September 2024 | 1.1 | Corrected link up diagram. (DOC-2043) |
| July 2024 | 1.0 | Initial release. |