Hot Reset

During a hot reset, the PCIe Controller, except sticky registers, undergoes a reset. The rest of the FPGA remains operational.

In root port mode, the HOT_RESET_IN input initiates a hot reset sequence on the PCIe link. The root port application can assert and hold HOT_RESET_IN high until the LINK_DOWN_RESET_OUT output goes high.
In endpoint mode, asserting LINK_DOWN_RESET_OUT triggers a hot reset.

When you trigger a hot reset, the PCIe Controller issues a reset request to soft logic and IP cores connected to it. Your user application must observe the reset handshake, and return a relevant RESET_ACK to allow the PCIe Controller to complete the hot reset procedure.