AXI Master Interface Signals

Table 1. AXI Master Write Address Channel
Signal Direction Width Clock Domain Description
TARGET_AXI_AWREADY Input 1 AXI_CLK Ready signals from the client to the PCIe Controller indicating that the application is ready to sample the address and associated parameters from the target write interface. The address and associated parameters are transferred across the interface when TARGET_AXI_AWVALID and TARGET_AXI_AWREADY are both high in a clock cycle.
TARGET_AXI_AWADDR Output 64 AXI_CLK The PCIe Controller places the address of the first byte in a burst when initiating a write transaction on the target write interface. The address is valid when TARGET_AXI_AWVALID is asserted. The AXI address is the starting byte-level address of the memory block or I/O location to be read or written. When the transaction is a 32-bit read/write, bits [63:32] are set to zeroes.
TARGET_AXI_AWID Output 8 AXI_CLK This output contains an 8-bit tag to identify the write transaction. This output is valid when TARGET_AXI_AWVALID is asserted.
TARGET_AXI_AWLEN Output 8 AXI_CLK Indicates the number of beats (data transfer cycles) associated with the current burst (0000 = 1 beat, 0001 = 2 beats, ..., 1111 = 16 beats). This information is valid when TARGET_AXI_AWVALID is asserted. The valid bytes within each beat are identified by the write strobe signal TARGET_AXI_WSTRB[7:0].
TARGET_AXI_AWSIZE Output 3 AXI_CLK Indicates the size of the AXI transfer.
TARGET_AXI_AWUSER Out 88 AXI_CLK
Sideband status information for inbound AXI write transfer.
[2:0] Transaction type:
010: Memory write
011: I/O write
All other values are reserved.
[5:3] PCIe attributes associated with the request.
[21:6]: PCI Requester ID associated with the request. With the legacy interpretation of RIDs, these 16 bits are divided into:
  • [31:24] an 8-bit bus number
  • [23:19] 5-bit device number
  • [18:16] 3-bit function number
When ARI is enabled, bits [31:24] carry the 8-bit bus number and [23:16] provide the function number.
[29:22] Request's PCI tag.
[32:30] Request's PCIe transaction class (TC).
[35:33] For memory and I/O requests, these bits identify the matching BAR for the memory or I/O address.
For 64-bit transactions, the BAR number is given as the lower address of the matching pair of BARs (i.e., 0, 2 or 4).1
000: BAR 0
001: BAR 1
010: BAR 2
011: BAR 3
100: BAR 4
101: BAR 5
110: Expansion ROM access.
For message requests, these bits provide the 3-bit Routing field r[2:0] from the message header.
[43:36] Request's target function determined by the BAR check. When ARI is in use, all 8 bits of this field are valid. Otherwise, only bits [50:48] are valid. This field is valid only for memory and I/O requests and is set to 0 for message requests.2
[51:44] For message requests, these bits provide the message code from the message TLP header. These bits are reserved for all other request types.
[59:52] 8-bit steering tag for the hint.
[61:60] Value of PH[1:0] associated with the hint.
[62] Set when the request has a transaction processing hint associated with it.
[64:63] PCIe AT bits:
00: Untranslated
01: Translation request
10: Translated
11: Reserved
[65] PASID present.
[85:66] PASID value, 20 bits maximum. The size depends on the Max PASID Width field in the PASID Capability Register.
[86] Privilege mode access.
[87] Execute mode access.
TARGET_AXI_AWVALID Output 1 AXI_CLK Valid signal for the address and control information on the AXI slave write interface. The PCIe Controller keeps this valid signal asserted until the client sets the ready input to the PCIe Controller (TARGET_AXI_AWREADY) in response.
Table 2. AXI Master Write Data Channel
Signal Direction Width Clock Domain Description
TARGET_AXI_WREADY Input 1 AXI_CLK Ready for write data from the client to the PCIe Controller. The client must assert this signal when it is ready to receive the next beat from the PCIe Controller.
TARGET_AXI_WDATA Output 256 AXI_CLK Data associated with a memory write operation delivered from the PCIe Controller. Data is transferred in little-endian order. For writes, data is transferred aligned. The data on this bus is valid when TARGET_AXI_WVALID is high.
TARGET_AXI_WDATA_PAR Output 32 AXI_CLK Contains the end-to-end parity for TARGET_AXI_WDATA. Odd parity is computed for every byte of the data and propagated through the PCIe Controller for end-to-end parity protection.
TARGET_AXI_WLAST Output 1 AXI_CLK Asserted in the last beat of the burst to indicate the end of the write transaction.
TARGET_AXI_WSTRB Output 32 AXI_CLK
Indicates valid bytes in the first and last beat of the data block being transferred. Data is transferred aligned.
Indicates valid bytes of the data block being transferred. The AXI interface supports noncontiguous byte enables on any data block. The AXI logic splits the write packets based on the write strobes, followimg the PCIe first/last byte enable as described in the specification.
TARGET_AXI_WSTRB_PAR Output 4 AXI_CLK Contains the end-to-end parity for TARGET_AXI_WSTRB.
TARGET_AXI_WVALID Output 1 AXI_CLK The PCIe Controller maintains data on the bus until the client has asserted TARGET_AXI_WREADY.
Table 3. AXI Master Write Response Channel
Signal Direction Width Clock Domain Description
TARGET_AXI_BID Input 8 AXI_CLK This output contains an 8-bit tag to identify the response phase of a write transaction. This output is valid when TARGET_AXI_BVALID is asserted.
TARGET_AXI_BID_PAR Input 1 AXI_CLK Contains the end-to-end parity for TARGET_AXI_BID.
TARGET_AXI_BRESP Input 2 AXI_CLK Indicates the response to the transaction when TARGET_AXI_BVALID is asserted.
TARGET_AXI_BRESP_PAR Input 1 AXI_CLK Contains the end-to-end parity for TARGET_AXI_BRESP.
TARGET_AXI_BVALID Input 1 AXI_CLK Valid for write response from client to PCIe Controller.
TARGET_AXI_BREADY Output 1 AXI_CLK Ready for write response from PCIe Controller to client. Client should hold the response signals and valid until this signal is asserted.
Table 4. AXI Master Read Address Channel
Signal Direction Width Clock Domain Description
TARGET_AXI_ARREADY Input 1 AXI_CLK Ready signals from the client to the PCIe Controller indicating that the application is ready to sample the address and associated parameters from the target read interface. The address and associated parameters are transferred across the interface when TARGET_AXI_ARVALID and TARGET_AXI_READ_ARREADY are both high in a clock cycle.
TARGET_AXI_ARADDR Output 64 AXI_CLK Address of the first byte in the read request. The address is valid when TARGET_AXI_ARVALID is asserted. The AXI address is the starting byte-level address of the memory block or I/O location to be read or written. When the transaction is a 32-bit read/write, bits [63:32] are set to zeroes.
TARGET_AXI_ARID Output 8 AXI_CLK
Read ID tag associated with the target memory read transaction. The client must store this tag and return it on TARGET_AXI_RID while transferring the data associated with the read request.
This output is valid when TARGET_AXI_ARVALID is asserted.
TARGET_AXI_ARLEN Output 8 AXI_CLK Indicates the number of beats (data transfer cycles) associated with the read burst.
TARGET_AXI_ARSIZE Output 3 AXI_CLK Indicates size of the AXI transfer.
TARGET_AXI_ARUSER Output 88 AXI_CLK
Sideband status information for inbound AXI read transfer.
For 64-bit transactions, the BAR number is given as the lower address of the matching pair of BARs (that is, 0, 2 or 4).
[2:0] Transaction type:
000: memory read
001: I/O read
All other values are reserved.
[5:3] Request's PCIe attributes associated.
[21:6] PCI Requester ID associated with the request. With the legacy interpretation of RIDs, these 16 bits are divided into:
  • [21:14] 8-bit bus number
  • [13:9] 5-bit device number
  • [8:6] 3-bit function number
When ARI is enabled, bits [21:14] carry the 8-bit bus number and bits [13:6] provide the function number.
[29:22] PCI Tag associated with the request.
[32:30] Request's PCIe transaction class (TC).
[35:33] For memory and I/O requests, these bits identify the matching BAR for the memory or I/O address.3
000: BAR 0
001: BAR 1
010: BAR 2
011: BAR 3
100: BAR 4
101: BAR 5
110: Expansion ROM access
[43:36] Request's target function number as determined by the BAR check. When ARI is in use, all 8 bits of this field are valid. Otherwise, only bits [50:48] are valid. This field is valid only for memory and I/O requests, and is set to 0 for message requests.4
[51:42] These bits are reserved for all read request types.
[59:52] 8-bit steering tag for the hint.
[61:60] Value of PH[1:0] associated with the hint.
[62] Set when the request has a transaction processing hint associated with it.
[64:63] PCIe AT bits:
00: Untranslated
01: Translation request
10: Translated
11: Reserved
[65] PASID present.
[85:66] PASID value, 20 bits maximum. The size depends on the Max PASID Width field in the PASID Capability Register.
[86] Privilege mode access.
[87] Execute mode access.
TARGET_AXI_ARVALID Output 1 AXI_CLK Valid signal for the address and control information on the AXI slave read interface. The PCIe Controller keeps this valid signal asserted until the client application sets the ready input to the PCIe Controller TARGET_AXI_ARREADY in response.
Table 5. AXI Master Read Data Channel
Signal Direction Width Clock Domain Description
TARGET_AXI_RDATA Input 256 AXI_CLK
Data associated with a memory read operation delivered by the client to the PCIe Controller. Data is transferred in little-endian order.
For memory reads, data is transferred in aligned fashion. The data on this bus is valid when TARGET_AXI_RVALID is high.
TARGET_AXI_RDATA_PAR Input 32 AXI_CLK Contains the end-to-end parity for TARGET_AXI_RDATA.
TARGET_AXI_RID Input 6 AXI_CLK When transferring data in response to a read request, the client must place the 6-bit read ID tag associated with the request on this bus. This tag must be valid when TARGET_AXI_READ_RVALID is high.
TARGET_AXI_RID_PAR Input 1 AXI_CLK Contains the end-to-end parity for TARGET_AXI_RID.
TARGET_AXI_RLAST Input 1 AXI_CLK The client must assert this signal in the last beat of the burst to indicate the end of the read burst.
TARGET_AXI_RRESP Input 2 AXI_CLK
Read status from client. Allowed status encoding are:
00: Good completion
10: Slave error
Others: Not supported
The PCIe Controller responds to the slave error by sending a completion on the link with the completer abort status, instead of a normal completion.
The read response status must be valid when TARGET_AXI_RVALID is high.
TARGET_AXI_RRESP_PAR Input 1 AXI_CLK Contains the end-to-end parity for TARGET_AXI_RRESP.
TARGET_AXI_RVALID Input 1 AXI_CLK Indicates valid data on the TARGET_AXI_RDATA bus. The client must maintain data on the bus until the PCIe Controller has asserted TARGET_AXI_RREADY.
TARGET_AXI_RREADY Output 1 AXI_CLK Ready for read data from the PCIe Controller to the client. The PCIe Controller asserts this signal when it is ready to receive the next beat from the client.
Table 6. AXI Master Sideband Signals
Signal Direction Width Clock Domain Description
TARGET_NON_POSTED_REJ Input 1 AXI_CLK Asserted by client when it cannot service a non-posted request. The PCIe Controller does not present any non-posted requests that it receives from the PCIe link. Instead, it will holds them in the PNP FIFO RAM until the signal is de-asserted.
If a non-posted TLP has already been queued from the PNP FIFO and this signal is asserted, the PCIe Controller places it on the AXI bridge. The client must accept the non-posted TLP. The in-flight non-posted TLPs in the PCIe Controller from the PNP FIFO cannot be stopped. However, non-posted TLPs that are in the PNP FIFO RAM when this signal is asserted or that come in after the signal is asserted are not forwarded to the AXI interface.
The client must assert this signal when it still can process two or three non-posted TLPs. This requirement allows posted TLPs to go past non-posted TLPs at the AXI master write interface due to client not being able to service non-posted TLPs.
1 This description is also applicable for root ports. If RC BAR check is enabled, 000 = RC BAR0 and 001 = RC BAR2 for the two RC 64-bit BARs.
2 This signal is applicable to endpoints only. For root ports, these bits are 0.
3 This description is also applicable to root ports. The BAR check is enabled, 000 = root port BAR0, 001 = root port BAR2 for the 2 root port 64-bit BARs.
4 This signal is applicable to endpoints only. For root ports, these bits are 0.