Non-Contiguous Reads

The AXI master interface does not distinguish between memory read requests received from the link with non-contiguous byte enables versus contiguous byte enables. The PCIe Controller presents a single DWORD, non-contiguous read on the AXI master interface with TARGET_AXI_ARLEN = 3'b0 and TARGET_AXI_ARSIZE = 3'b010. A two DWORD non-contiguous read can be presented on the AXI master interface with TARGET_AXI_ARLEN equal to 3'b000 or 3'b001, depending on the address alignment of the read request with respect to the 256-bit AXI data bus. In either case, the TARGET_AXI_ARSIZE is 3'b011. The user must implement memory reads free of side effects so that an entire word can be read from memory without side effects even when only a part of the word is requested by the read transaction.