L1.2 Operation

The following figure illustrates the sequence for the L1 PM substates state machine to enter the L1.2 substate.

Attention: You can enable L1.1 in the Interface Designer (PCI Express block > Pins tab > Power Management sub-tab > PM L1.2 Substate Enable).
It is possible to enable/disable L1.2 with the APB interface, however, you must follow the rules described in L1 Substate Register Programming for the power transitions to work correctly.
Figure 1. L1.2 Substate Entry

If the entry conditions for L1.2 are satisfied, it first performs the handshake with the PHY using the PHY_ENT_L1_X and PHY_ACK_L1_X signals to prepare the PHY for the removal of the reference clock. Once the PHY has asserted PHY_ACK_L1_X, the PCIe Controller de-asserts CLKREQ_OUT_N. If the link partner also de-asserts its CLKREQ# output, the core clock becomes inactive and the PCIe Controller's CLKREQ_IN_N input is de-asserted. The L1 PM substates state machine transitions to L1.2.Entry when the CLKREQ_IN_N input goes high. While the L1 PM substates state machine is in the L1.2.Entry substate, it monitors the CLKREQ_IN_N input and transitions back to L1.0 if it is asserted. If CLKREQ_IN_N remains de-asserted, the state machine stays in the L1.2.Entry substate for an interval TPOWER_OFF (2 ms) and then transitions to L1.2.Idle.

When the L1 PM substates state machine is in L1.2.Idle, the client or the link partner can initiate a transition of the link out of the L1-substate. The following figure shows the operation of the L1.2 substates when there is an exit trigger from the client. CLIENT_REQ_EXIT_L1 represents all local exit triggers.

Figure 2. L1.2 Substate Locally Initiated Exit

Any one of the local exit triggers initiates the L1.2 exit process. The PCIe Controller first asserts CLKREQ_OUT_N to turn on the core clock, resulting in CLKREQ_IN_N becoming asserted. When CLKREQ_IN_N goes low, the L1 PM substates state machine transitions to L1.2.Exit.

While in L1.2.Exit, the L1 PM substates state machine performs the PHY_ENT_L1_X/ PHY_ACK_L1_X handshake with the PHY to prepare the PHY for the re-introduction of the clocks, and subsequently transitions back to L1.0. The L1 PM substates state machine must stay in L1.2.Exit for a minimum interval of TPOWER_ON. The duration of this interval is determined by the setting of the TPOWER_ON value and scale parameters in the L1 PM Substates Control 2 Register. The interval can vary from 0 to 3,100 ms.

Figure 3. L1.2 Substate Exit Initiated by Link Partner

The previous figure illustrates the operation when the link partner initiates the exit from L1. When in L1.2.Idle, the link partner initiates the transition of the link from L1 by asserting its CLKREQ# output, resulting in the assertion of the PCIe Controller's CLKREQ_IN_N input. When CLKREQ_IN_N goes low, the L1 PM substates state machine transitions to L1.2.Exit (after satisfying the minimum 4 μs stay in L1.2.Idle). After completing the handshake with the PHY for re-enabling its clocks and staying in L1.2.Exit for a minimum interval of TPOWER_ON, the L1 PM substates state machine then transitions to L1.0.