AXI Region Base Address Registers

The PCIe Controller uses region select logic to match the outbound AXI address and the pre-programmed AXI address (in the AXI region base address registers for each region) to determine the region to which it belongs. The matching is done from region 0 to <max regions> - 1. The comparator selects the first matching region as the region number used to pick the static TLP information (PCIe descriptor) as well as the PCIe address (for address translation). The AXI region sizes and region base addresses are programmable.

Table 1. AXI Region Base Address Registers

Register	Bits	Allocation	Default
axi_addr1	31:0	Upper [63:32] bits of the AXI region base address.	32'd0
axi_addr0	31:8	Lower [31:8] bits of the AXI region base address.	24'd0
	7:6	Reserved	2'd0
	5:0	The programmed value in this field + 1 gives the region size. The minimum value to be programmed into this field is 7 because the lower 8 bits of the AXI region base address are replaced by zeros by the region select logic. The minimum region size is 256 bytes.	6'd0

All AXI regions has their start address aligned to the region size, which is programmed through the AXI Region Base Address Register axi_addr0 [5:0]. If the select logic does not find a match, the PCIe Controller responds with a DEC ERR over the AXI interface.