AXI Master and Slave Read/Write Length Limitations

For outbound transfers:

  • Reads are limited by minimums (AXI_SLAVE_MAX_RD_TRANSFER_SIZE, MAX_READ_REQUEST_SIZE). The PCIe Controller AXI bridge cannot handle read requests if the outbound read request length is greater than MAX_READ_REQUEST_SIZE.
  • Writes are limited by AXI_SLAVE_MAX_WR_TRANSFER_SIZE. If AXI_SLAVE_MAX_WR_TRANSFER_SIZE is greater than MAX_PAYLOAD _SIZE—and the outbound write request length is greater than MAX_PAYLOAD _SIZE—the write requests are split at MAX_PAYLOAD_SIZE boundary.

For inbound transfers:

  • Writes are limited by MAX_PAYLOAD_SIZE. If AXI_MASTER_MAX_WR_TRANSFER_SIZE is less than MAX_PAYLOAD_SIZE and the inbound packet length is greater than AXI_MASTER_MAX_WR_TRANSFER_SIZE, requests are split into AXI_MASTER_MAX_WR_TRANSFER_SIZE packets. The same AXI ID is assigned to all split packets.
  • Reads are limited by MAX_READ_REQUEST_SIZE. If AXI_MASTER_MAX_RD_TRANSFER_SIZE is less than MAX_READ_REQUEST_SIZE and the inbound packet length is greater than AXI_MASTER_MAX_RD_TRANSFER_SIZE, requests are split into min(AXI_MASTER_MAX_RD_TRANSFER_SIZE, MAX_PAYLOAD_SIZE) packets. The same AXI ID is assigned to all split packets. The splits measure a length of min(AXI_MASTER_MAX_RD_TRANSFER_SIZE, MAX_PAYLOAD_SIZE). The start address is aligned to an RCB boundary and the next address is calculated by adding min(AXI_MASTER_MAX_RD_TRANSFER_SIZE, MAX_PAYLOAD_SIZE).
Note: MAX_PAYLOAD_SIZE and MAX_READ_REQUEST_SIZE are host-configured values in the device control register.
AXI_MASTER_MAX_RD_TRANSFER_SIZE, AXI_MASTER_MAX_WR_TRANSFER_SIZE are the maximum transfer sizes for the AXI master.
AXI_SLAVE_MAX_RD_TRANSFER_SIZE, AXI_SLAVE_MAX_WR_TRANSFER_SIZE are the maximum transfer sizes for the AXI slave.