Introduction
Features
Functional Description
Clock Sources
Link Control
Power Management
Configuring Registers with the APB Interface
Configuration Snoop Interface
Vendor-Specific Extended Capability (VSEC)
Configuration Guide
Managing Outbound NP Outstanding Requests and Completion Responses (Endpoint)
Interface Signals
Appendix A: Acronyms and Abbreviations
Appendix B: Error Handling
Appendix C: LTSSM State Encoding
Appendix D: PCIe Configuration Capabilities Linked List
- Configuration-Specific Capabilities
Appendix E: Supported Chipsets
Appendix E: Skew
Appendix F: Hot Plug Support
Revision History

Interface Signals

The following topics describe the PCIe Controller signal interface. Refer to Figure 2 for the block diagram.

Clock Signals
Reset Interface Signals
AXI Master Interface Signals
AXI Slave Interface Signals
Interrupt Interface Signals
Message Interface Signals
Status and Error Indicator Signals
Function-Level Reset Signals
Configuration Snoop Interface Signals
Vendor Specific (VSEC) Interface Signals
Power Management Interface Signals
L1 Interface Signals
L1 Substate Interface Signals
Hot Plug Interface Signals
APB Interface Signals