AXI Slave Interface Signals

Table 1. AXI Slave Interface Write Address Channel
Signal	Direction	Width	Clock Domain	Description
MASTER_AXI_AWADDR	Input	64	AXI_CLK	Address for the master-side write transaction from the client. The address is valid when MASTER_AXI_AWVALID is asserted. The AXI address is the starting byte-level address of the memory block, config or I/O location to be read or written. When the transaction is a 32-bit read/write, bits [63:32] must be set to zeroes.
MASTER_AXI_AWID	Input	8	AXI_CLK	The client must place a 8-bit identifier for the write transaction on this input. This tag is used to match the write completion status returned by the PCIe Controller with the associated request. This input must be valid when MASTER_AXI_AWVALID is asserted.
MASTER_AXI_AWLEN	Input	8	AXI_CLK	Indicates the number of beats (data transfer cycles) associated with the current burst. This information is valid when MASTER_AXI_AWVALID is asserted. The valid bytes within each beat are identified by the write strobe signal MASTER_AXI_WSTRB.
MASTER_AXI_AWSIZE	Input	3	AXI_CLK	Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
MASTER_AXI_AWUSER	Input	88	AXI_CLK	Sideband descriptor. Refer to AXI Outbound Access through Sideband Descriptor for detailed description.
MASTER_AXI_AWVALID	Input	1	AXI_CLK	Valid signal for the address and other parameters associated with the request on the AXI master write interface. The client must keep this valid signal asserted until the PCIe Controller sets the ready output (MASTER_AXI_AWREADY) in response.
MASTER_AXI_AWREADY	Output	1	AXI_CLK	Ready signal from the PCIe Controller to the client, indicating that the PCIe Controller is ready to sample the address and associated parameters from the master write interface. The address and associated parameters are transferred across the interface when MASTER_AXI_AWVALID and MASTER_AXI_AWREADY are both high in a clock cycle.

Table 2. AXI Slave Interface Write Data Channel
Signal	Direction	Width	Clock Domain	Description
MASTER_AXI_WDATA	Input	256	AXI_CLK	Data associated with a memory write operation delivered from the client to the PCIe Controller. Data is transferred in little-endian order. For memory writes, data is transferred in aligned fashion. The data on this bus is valid when MASTER_AXI_WVALID is high.
MASTER_AXI_WDATA_PAR	Input	32	AXI_CLK	Contains the end-to-end parity for MASTER_AXI_WDATA.
MASTER_AXI_WLAST	Input	1	AXI_CLK	Asserted in the last beat of the burst to indicate the end of the write transaction.
MASTER_AXI_WSTRB	Input	32	AXI_CLK	Indicates valid bytes in the first and last beat of the data block being transferred. Data is transferred in aligned fashion. For write transactions with a payload size of 8 bytes or less, the byte strobes may be non-contiguous, as described in the PCIe specification.
MASTER_AXI_WSTRB_PAR	Input	4	AXI_CLK	Indicates valid bytes in the first and last beat of the data block being transferred. Data is transferred aligned. For write transactions with a payload size of 8 bytes or less, the byte strobes may be non-contiguous, as described in the PCIe Specifications.
MASTER_AXI_WVALID	Input	1	AXI_CLK	Indicates valid data on the MASTER_AXI_WDATA bus. The client must maintain data on the bus until the PCIe Controller has asserted MASTER_AXI_WREADY in return.
MASTER_AXI_WREADY	Output	1	AXI_CLK	Ready for write data from the PCIe Controller to the client. The core asserts this signal when it is ready to receive the next beat from the client.

Table 3. AXI Slave Interface Write Response Channel
Signal	Direction	Width	Clock Domain	Description
MASTER_AXI_BREADY	Input	1	AXI_CLK	Ready for write response from the PCIe Controller to the client. The client asserts this signal when it is ready to accept the next write response from the client
MASTER_AXI_BID	Output	8	AXI_CLK	For each write transaction received on the AXI master write interface, the PCIe Controller returns the completion status of the transaction by placing the 8-bit identifier of this transaction and asserting MASTER_AXI_BVALID.
MASTER_AXI_BID_PAR	Output	1	AXI_CLK	Contains the end-to-end parity for MASTER_AXI_BID. Odd parity is computed for every byte of the data and propagated through the PCIe Controller for end-to-end parity protection.
MASTER_AXI_BRESP	Output	2	AXI_CLK	Write completion status from client. Valid status encoding are: 2'b00: Good completion 2'b10: Slave error, Completion error for Non-Posted Writes 2'b11: Decode error
MASTER_AXI_BRESP_PAR	Output	1	AXI_CLK	Contains the end-to-end parity for MASTER_AXI_BRESP. Odd parity is computed for every byte of the data and propagated through the PCIe Controller for end-to-end parity protection.
MASTER_AXI_BUSER	Output	5	AXI_CLK	[2:0] Completion error code. [4:3] Completion status code. Other fields are reserved. See Appendix B: Error Handling.
MASTER_AXI_BUSER_PAR	Output	1	AXI_CLK	Contains the end-to-end parity for MASTER_AXI_BUSER. Odd parity is computed for every byte of the data and propagated through the PCIe Controller for end-to-end parity protection.
MASTER_AXI_BVALID	Output	1	AXI_CLK	The PCIe Controller asserts this output when it has placed the completion status of a master write transaction on MASTER_WRITE_COMPLETION_STATUS. It keeps the output asserted until the client has asserted MASTER_AXI_BREADY.

Table 4. AXI Slave Interface Read Address Channel
Signal	Direction	Width	Clock Domain	Description
MASTER_AXI_ARADDR	Input	64	AXI_CLK	Address for the client's master-side read transaction. The client must places the address of the first byte of the burst on this bus when initiating a read transaction on the master read interface. The address is valid when MASTER_AXI_ARVALID is asserted.
MASTER_AXI_ARID	Input	8	AXI_CLK	Read ID tag associated with the master memory read transaction. This tag is used to match the read completion status returned by the PCIe Controller with the associated request. This output must be valid when MASTER_AXI_ARVALID is asserted.
MASTER_AXI_ARLEN	Input	8	AXI_CLK	Indicates the number of beats (data transfer cycles) associated with the read burst. This information is valid when MASTER_AXI_ARVALID is asserted.
MASTER_AXI_ARSIZE	Input	3	AXI_CLK	Burst size. This signal indicates the size of each transfer in the burst. All bytes in the current transfer size are read.
MASTER_AXI_ARUSER	Input	88	AXI_CLK	Sideband descriptor. AXI Outbound Access through Sideband Descriptor” for detailed description.
MASTER_AXI_ARVALID	Input	1	AXI_CLK	Valid signal for the address and associated parameters on the AXI master read interface. The client must keep this valid signal asserted until the PCIe Controller sets the ready input (MASTER_AXI_ARREADY).
MASTER_AXI_ARREADY	Output	1	AXI_CLK	Ready signal from the PCIe Controller to the client, indicating that the PCIe Controller is ready to sample the address and associated parameters from the master read interface. The address and associated parameters are transferred across the interface when MASTER_AXI_ARVALID and MASTER_AXI_ARREADY are both high in a clock cycle.

Table 5. AXI Slave Interface Read Data Channel
Signal	Direction	Width	Clock Domain	Description
MASTER_AXI_RREADY	Input	1	AXI_CLK	Ready for read response status from the client. The client must assert this signal when it ready to accept the read response status from the PCIe Controller. PCIe Controller core keeps MASTER_AXI_RVALID asserted until it samples this ready signal high on a positive edge of the clock.
MASTER_AXI_RDATA	Output	256	AXI_CLK	Data associated with a memory read operation delivered by the PCIe Controller to the client. Data is transferred in little-endian order. Data is transferred in aligned fashion. The data on this bus is valid when MASTER_AXI_RVALID is high.
MASTER_AXI_RDATA_PAR	Output	32	AXI_CLK	Contains the end-to-end parity for MASTER_AXI_RDATA. Odd parity is computed for every byte of the data and propagated through the PCIe Controller for end-to-end parity protection.
MASTER_AXI_RID	Output	8	AXI_CLK	The PCIe Controller places the 4-bit read ID tag associated with the read request when returning data/completion status to the client. The ID on this bus is valid when MASTER_READ_REPONSE_VALID is high.
MASTER_AXI_RID_PAR	Output	1	AXI_CLK	Contains the end-to-end parity for MASTER_AXI_RID. Odd parity is computed for every byte of the data and propagated through the PCIe Controller for end-to-end parity protection.
MASTER_AXI_RLAST	Output	1	AXI_CLK	The PCIe Controller asserts this signal in the last beat of the burst to indicate the end of the read burst.
MASTER_AXI_RRESP	Output	2	AXI_CLK	Read completion status from client. Valid status encoding are: 2'b00: Good completion 2'b10: Slave error, completion error 2'b11: Decode error
MASTER_AXI_RRESP_PAR	Output	1	AXI_CLK	Contains the end-to-end parity for MASTER_AXI_RRESP.. Odd parity is computed for every byte of the data and propagated through the PCIe Controller for end-to-end parity protection.
MASTER_AXI_RUSER	Output	7	AXI_CLK	[2:0] Completion error code. [4:3] Completion status code. [5] If 1, uncorrectable error in the AXI reorder RAM or completion RAM. [6] If 1, AXI slave read/write addresses may not match any of the AXI base address programmed in the outbound region. See Appendix B: Error Handling.
MASTER_AXI_RUSER_PAR	Output	1	AXI_CLK	Contains the end-to-end parity for MASTER_AXI_RUSER. Odd parity is computed for every byte of the data and propagated through the PCIe Controller for end-to-end parity protection.
MASTER_AXI_RVALID	Output	1	AXI_CLK	Valid for read response status from the PCIe Controller to the client. The assertion of this signal indicates that the PCIe Controller is ready to transfer data in response to a read request it received from the client.