Status and Error Indicator Signals

Table 1. Status and Error Indicator
Signal Name	Direction	Width	Clock Domain	Descriptions
LTSSM_STATE	Output	6	AXI_CLK	LTSSM state.
REG_ACCESS_CLK_SHUTOFF	Output	1	USER_APB_CLK	Pulse indicating an APB access when the internal core clock was not running.
CORE_CLK_SHUTOFF	Output	1	USER_APB_CLK	Level signal indicating that the core clock is not running.
LINK_STATUS	Output	2	AXI_CLK	Status of the PCIe link. 00: No receivers detected. 01: Link training in progress. 10: Link up, DL initialization in progress. 11: Link up, DL initialization completed.
FUNCTION_STATUS	Output	16	AXI_CLK	These outputs indicate the states of each function's command register bits in the PCI configuration space. Used to enable requests and completions from the host. [0] Function 0 I/O space enable [1] Function 0 memory space enable [2] Function 0 bus master enable [3] Function 0 INTx disable [4] Function 1 I/O space enable [5] Function 1 memory space enable [6] Function 1 bus master enable [7] Function 1 INTx disable and so on.
PCIE_MAX_READ_REQ_SIZE	Output	3	AXI_CLK	The maximum request size field programmed in the PCI Express Device Control Register. When using multiple functions, this output provides the minimum of the maximum read-request field in the PFs' Device Control Registers. The client must limit the size of outgoing read requests to this value. The 3-bit codes are the same as those defined in the PCIe specifications: 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1,024 bytes 100: 2,048 bytes 101: 4,096 bytes
PCIE_MAX_PAYLOAD_SIZE	Output	3	AXI_CLK	The maximum payload size field programmed in the PCI Express Device Control Register. When using multiple fuctions, this output provides the minimum of the maximum payload-size field in the PFs' Device Control Registers. The client must limit the size of outputgoing completion payloads to this value. The 3-bit codes are the same as those defined in the PCIe specifications: 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes
ATS_PR_CONTROL_REG_RESET	Output	4	AXI_CLK	Reset per PF. When the enable field is clear (or is being cleared during the same register update that sets this field) writing a 1b to this field clears the associated implementation dependent page request credit counter and pending request state for the associated page request interface. If this field is written with 0b or if it is written with any value while the enable field is set, no action is taken. Reads of this field return 0b.
ATS_PR_CONTROL_REG_ENABLE	Output	4	AXI_CLK	Indicates that the page request interface can to make page requests. If this field is clear, the page request interface is not allowed to issue page requests. If this field and the stopped field are both clear, the page request interface does not issue new page requests. Instead, it has outstanding page requests that have been transmitted or are queued for transmission. When the page request interface is transitioned from not-enabled to enabled, its status flags (stopped, response failure, and unexpected response flags) are cleared. Enabling a page request interface that has not successfully stopped has indeterminate results. Default value is 0b.
Q0_PMA_CMN_READY	Output	1	Async	Common ready.
Q0_PIPE_P00_RATE	Output	2	Static	PIPE link signaling rate. Selects the data rate. 2'b00: PCIe Gen1 2'b01: PCIe Gen2 2'b10: PCIe Gen3 2'b11: PCIe Gen4
CORRECTABLE_ERROR_IN	Input	1	AXI_CLK	The client can activate this input for one clock cycle to indicate that the client detected a correctable error that needs to be reported as an internal error through using PCIe advanced error reporting. In response, the PCIe Controller sets the Corrected Internal Error Status bit in the enabled function(s)' AER Correctable Error Status Register. In endpoint mode it also sends an error message if enabled to do so. This error is not function specific.
UNCORRECTABLE_ERROR_IN	Input	1	AXI_CLK	The client can activate this input for one clock cycle to indicate that the client detected an uncorrectable error that needs to be reported as an internal error through using PCIe advanced error reporting. In response, the PCIe Controller sets the Uncorrected Internal Error Status bit in the enabled function(s)' AER Correctable Error Status Register. In endpoint mode it also sends an error message if enabled to do so. This error is not function specific.
FATAL_ERROR_OUT	Output	1	AXI_CLK	This output is a single clock cycle for endpoints. Endpoints: The PCIe Controller activates this output for one clock cycle when it detects a fatal error and its reporting is not masked. When using multiple functions, it is the logical OR of the fatal error status bits in the function(s)' Device Status Registers.
NON_FATAL_ERROR_OUT	Output	1	AXI_CLK	This output is a single clock cycle for endpoints. Endpoints: The PCIe Controller activates this output for one clock cycle when it detects a non-fatal error and its reporting is not masked. When using multiple functions, it is the logical OR of the non-fatal error status bits in the function(s)' Device Status Registers.
CORRECTABLE_ERROR_OUT	Output	1	AXI_CLK	This output is a single clock cycle for endpoints. Endpoints: The PCIe Controller activates this output for one cycle when it detects a correctable error and its reporting is not masked. When using multiple functions, it is the logical OR of the correctable error status bits in the function(s)' Device Status Registers.
PHY_INTERRUPT_OUT	Output	1	AXI_CLK	Active-high, level-interrupt output. The PCIe Controller asserts this output in the root port mode to signal a link training-related event: Local change: The link bandwidth changed because the link width or operating speed changed, and the change was initiated locally (not by the link partner) without the link going down. This interrupt is enabled by the Link Bandwidth Management Interrupt Enable bit in the Link Control Register. You can read the this interrupt's status in the Link Bandwidth Management Status bit of the Link Status Register. Automomous change: The link bandwidth changed autonomously because the link width or operating speed changed and the change was initiated by the remote node. This interrupt is enabled by the Link Autonomous Bandwidth Interrupt Enable bit in the Link Control Register. You can read this interrupt's status from the Link Autonomous Bandwidth Status bit of the Link Status Register. This signal is not active when the PCIe Controller is configured as an endpoint.