Configuration Snoop Interface Signals
| Signal | Direction | Width | Clock Domain | Description |
|---|---|---|---|---|
| CONFIG_READ_DATA | Input | 32 | AXI_CLK | The client can provide data from an externally implemented configuration register to the PCIe Controller using this bus. If the client has set CONFIG_READ_DATA_VALID, the PCIe Controller samples this data on the next positive clock edge after it sets CONFIG_READ_RECEIVED high. |
| CONFIG_READ_DATA_PAR | Input | 4 | AXI_CLK | Contains the end-to-end parity for CONFIG_READ_DATA. |
| CONFIG_READ_DATA_VALID | Input | 1 | AXI_CLK | The client asserts this input to the PCIe Controller to supply
data from an externally implemented configuration register. The PCIe Controller samples this input data on the next positive clock edge
after it sets CONFIG_READ_RECEIVED high. If the PCIe Controller
detects this input is asserted, it uses the data supplied on the CONFIG_READ_DATA
bus as the completion payload for the received configuration read request.
You can extend the timing of this signal by programming the Debug Mux
Control 2 Register. See Configuration Snoop Interface for
timing diagrams. |
| CONFIG_READ_RECEIVED | Output | 1 | AXI_CLK | The PCIe Controller generates a one clock cycle pulse on this output when receives a configuration read request from the link. |
| CONFIG_REG_NUM | Output | 10 | AXI_CLK | The 10-bit address of the configuration register being read or written. The data is valid when CONFIG_READ_RECEIVED or CONFIG_WRITE_RECEIVED is high. |
| CONFIG_WRITE_BYTE_ENABLE | Output | 4 | AXI_CLK | Byte enables for a configuration write transaction. |
| CONFIG_WRITE_BYTE_ENABLE_PAR | Output | 1 | AXI_CLK | Contains the end-to-end parity for CONFIG_WRITE_BYTE_ENABLE. |
| CONFIG_WRITE_DATA | Output | 32 | AXI_CLK | Data being written to a configuration register. This output is valid when CONFIG_WRITE_RECEIVED is high. |
| CONFIG_WRITE_DATA_PAR | Output | 4 | AXI_CLK | Contains the end-to-end parity for CONFIG_WRITE_DATA. |
| CONFIG_WRITE_RECEIVED | Output | 1 | AXI_CLK | The PCIe Controller generates a one clock cycle pulse on this output when it has received configuration write request from the link. |
| CONFIG_FUNCTION_NUM | Output | 8 | AXI_CLK | Function number. |