RX Margining PIPE Interface: Write Ack Timeout

During the execution of the GoToNormalSettings, ClearErrorLog, StepMarginTimingOffset or StepMarginVoltageOffset commands, the PCIe Controller issues a write committed command to the PHY over the PIPE interface and waits for the PHY to respond with WriteAck.

PCIe Controller waits for 10 ms to receive a WriteAck. If it is not received, the PCIe Controller reports an error in the Local Management Register Margining Error Status 2 Register.