Outbound PCIe Descriptor Registers

These registers hold the static information in the TLP (e.g., function number, requester ID, etc.).

Table 1. desc0: Outbound PCIe Descriptor Register for Different TLP Accesses
Bits Memory and I/O TLPs Configuration TLP Vendor-Defined Message TLP Normal Message TLP
3:0 Transaction type
0010: Memory I/O
0110: I/O
 Transaction type
1010: Type 0 configuration
1011: Type1 configuration
 Transaction type
1101: Vendor-defined message
 Transaction type
1100: Normal message
6:4 PCIe attributes
[6] ID-based ordering
[5] Relaxed ordering
[4] No snoop
 Same as Memory I/O TLP Same as Memory I/O TLP Same as Memory I/O TLP
8:7 ATS[1:0] Reserved Bit 8: Carries bit [64] of the vendor defined message header.
Bit 7: Reserved.
 Reserved for normal messages.
Bit 8: Carries bit [64] of the PRI message header.
15:9 Reserved Reserved Carries [71:65] of the vendor defined message header. Reserved for normal messages.
16 If desc0 [8:7] bits are set to 2'b01 (i.e., it is an ATS translation request) or if it is a memory read request, this bit is used as no write (NW) flag. In this case the address must be aligned (i.e., address bits 11:0 must be reserved as per the PCIe protocol specification). Reserved Reserved Reserved
19:17 PCIe traffic class PCIe traffic class PCIe traffic class PCIe traffic class
20 When the request is a memory write transaction, setting this bit causes the PCIe Controller to poison the memory write TLP being sent. This bit has no effect for other transactions. Reserved Reserved Reserved
21 Force ECRC insertion. Setting this bit to 1 forces the PCIe Controller to append a TLP digest containing ECRC to the TLP, even when ECRC is not enabled for the function generating the request. Same as Memory I/O TLP Same as Memory I/O TLP Same as Memory I/O TLP
22 Reserved Reserved Reserved Reserved
23 Enables the client to provide the bus and device numbers to be used in the requester ID.
0: The PCIe Controller uses the captured values of the bus and device numbers to form the Requester ID.
1: The PCIe Controller uses the bus and device numbers supplied by the client on desc1[7:0] and desc0[31:27] to form the requester ID.
This bit must always be set while originating requests in root port mode, and the corresponding bus and device numbers must be placed on desc1[7:0] and desc0[31:27].
 1: The PCIe Controller uses the bus and device numbers supplied by the client on addr0[27:20] and addr0[19:15] to form the completer ID.
This bit must always be set while originating requests in root port mode, and the corresponding bus and device numbers must be placed on addr0[27:20] and addr0[19:15].
 Same as Memory I/O TLP Same as Memory I/O TLP
31:24 PCI function number associated with the request.
ARI mode: All 8 bits are used to indicate the requesting function.
Non-ARI mode: Bits [26:24] represent the function number.
The client must always specify the function number regardless of the bit [23] setting.
Bits [31:27] specify the device number to be used within the requester ID, when bit [23] is set.
 Reserved Same as Memory I/O TLP Same as Memory I/O TLP
Table 2. desc1: Outbound PCIe Descriptor Register for Different TLP Accesses
Bits Memory and I/O TLPs Configuration TLP Vendor-Defined Message TLP Normal Message TLP
7:0 When desc0[23] is set, this field must specify the bus number to be used for the requester ID. Otherwise, this field is ignored. Reserved Same as Memory I/O TLP Same as Memory I/O TLP
31:8 Reserved Reserved Reserved Reserved
Table 3. desc2: Outbound PCIe Descriptor Register for Different TLP Accesses
Bits Memory and I/O TLPs Configuration TLP Vendor-Defined Message TLP Normal Message TLP
7:0
If index bit is 0 this value is taken as the TLP steering tag for the hint.
If index bit is 1, this value [7:0] is used as a pointer to the table holding the steering tag values.
 Reserved Reserved Reserved
8 Index bit Reserved Reserved Reserved
10:9 Value of PH [1:0] associated with the hint. Reserved Reserved Reserved
11 TPH length Reserved Reserved Reserved
12 Set when the request has a transaction processing hint associated with it. Reserved Reserved Reserved
20:13 Reserved Reserved Reserved Reserved
Table 4. desc3: Outbound PCIe Descriptor Register for Different TLP Accesses
Bits Memory and I/O TLPs Configuration TLP Vendor-Defined Message TLP Normal Message TLP
0 PASID present bit 1'b0 1'b0 1'b0
20:1 PASID value 20'd0 20'd0 20'd0
21 Privilege mode access requested 1'b0 1'b0 1'b0
22 Execute mode access requested 1'b0 1'b0 1'b0
31:23 Reserved Reserved Reserved Reserved