L1 Interface Signals
| Signal | Direction | Width | Clock Domain | Description |
|---|---|---|---|---|
| CLIENT_REQ_EXIT_L1 | Input | 1 | Async | Client logic can trigger an explicit L1 exit by asserting this signal. This
signal triggers an exit to L0 from L1 or from L1 substates. This signal can also be
used to block L1 entry in endpoint mode. You can drive this signal from the
PM_CLK, core clock, or AXI_CLK domain depending on your configuration. It
is synchronized inside the PCIe Controller before use. |