Step Margin Execution Status
The step margin execution status is updated when a write committed is received from the PHY. The 2-bit status is derived as shown in the following table.
| Inputs | Step Margin Execution Status [1:0] | Description |
|---|---|---|
| PHY issues Write_Ack in response to a write committed by the PCIe Controller to start margining. | 01 | 01b: Set up for margin in progress. The receiver is getting ready but has not yet started executing the step margin command. MErrorCount is 0. |
| PHY sets the Margin Status bit in RX Margin Status 0 PIPE MAC Register in response to a write committed by the PCIe Controller to start margining. | 10 | 10b: Margining in progress. The receiver is executing the step margin command. MErrorCount reflects the number of errors detected. |
| PHY sets the margin NAK bit in the RX Margin Status 0 PIPE MAC Register in response to a write committed by the PCIe Controller to start margining. | 11 | 11b: NAK. Indicates that an unsupported lane margining command was issued. For example, timing margin beyond +/- 0.2 UI. MErrorCount is 0. |
| PHY updates error count bits [5:0] by issuing a write committed to the MAC RX Margin Status 2 Register. When error count bits [5:0] is greater than error limit[5:0], update execution status. | 00 | 00b: Too many errors. The receiver autonomously went back to its default settings. MErrorCount reflects the number of errors detected. Note that MErrorCount might be greater than the error count limit. |