Data Link Layer

On the RX side, the data from the link passes through a decoder state machine for each link. The decoders verify the packet integrity by matching the received CRC with the generated CRC, and comparing their sequence numbers with the expected values (for TLPs). There is a separate CRC module for TLPs (32-bit CRC) and DLLPs (16-bit CRC).

After comparing and removing the link-layer CRC, the DLLP decoders pass the received packet to its target module based on the packet type. The DLLP decoders pass all TLPs they receive onto the the transaction layer (after first removing their sequence number and LCRC fields). The PCIe Controller processes data link layer acknowledgements (ACKs and NAKs) within the data link layer itself, and sends credit DLLPs to the flow control module.

After the CRC check, the PCIe Controller sends arriving data link layer acknowledgements to the transmit side for processing. Logic on the transmit side matches the acknowledgements with outstanding packets and handles any errors.

The receive side also generates acknowledgements (ACKs and NAKs) for the received TLPs. The PCIe Controller sends these packets to the transmit side where they are multiplexed with outgoing TLPs.

On the TX side, the PCIe Controller formats the received transaction layer data for transmission to the physical layer by inserting a sequence number and CRC. The PCIe Controller multiplexes the formatted TLPs with other outgoing DL packets—such as ACKs, NAKs, and credit packets—and sends them to the physical layer over a data path shared by both links.

The TX side also contains the replay buffer associated with the link. The reply buffer is responsible for re-transmitting packets when needed and uses an external single-port RAM for storing the packets. There is also an internal pointer RAM for keeping track of packets stored in the replay buffer.

The data link layer also generates power management DLLPs to facilitate transitions of the link to the L1 and L2 states.