Appendix D: PCIe Configuration Capabilities Linked List

The following figure shows the PCIe Controller Capabilities Linked List implementation. Note that:

  • Each bubble shows the address offset for each capability structure.
  • The address offsets are all 12 bits.
Figure 1. Configuration Capabilities

Some capability structures may not be selected in this configuration. In that case, the next capability pointer of the previous selected capability structure points to the next selected capability structure. For example, if DPA, SR-IOV, or TPH_REQ capabilities are not selected, the LTR_NEXT_CAPABILITY_POINTER points to the PCIe Secondary Extended Capability Structure.

Additionally, some capability structures are only visible to the host configuration software if the corresponding strap input is enabled.

  • ARI capability is visible only if the ARI_ENABLE strap input is 1.
  • SR-IOV Capability is visible only if the SR_IOV_ENABLE strap input is 1.

If these strap inputs are not enabled, the capability linked list is automatically modified to link the previous capability with the next capability. These strap inputs must be stable before deasserting RESET_N, MGMT_RESET_N, or MGMT_STICKY_RESET_N.