Outbound Access through the Sideband Descriptor

This topic describes how to send an AXI outbound address packet directly—without doing any address translation. This method is useful for dynamic address translations; that is, the client does not have enough time to program one of the 32 region registers.

In this method, the PCIe Controller drives the translated outbound PCIe address (PCIe descriptor) directly on MASTER_AXI_AWADDR and MASTER_AXI_ARADDR. It does not perform address translation performed on the AXI address. A sideband access enable bit in MASTER_AXI_AWUSER and MASTER_AXI_ARUSER gives the sideband access priority over the region access.

Table 1. AXI Slave Sideband Signal Description (MASTER_AXI_AWUSER and MASTER_AXI_ARUSER)
Bit	Memory or I/O TLP	Configuration TLP	Message TLP
3:0	Transaction type: 0000: Memory read 0010: Memory write 0110: I/O write 0100: I/O read All other values are reserved.	Transaction type: 1010: Type 0 configuration write 1000: Type 0 configuration read 1011: Type 1 configuration write 1001: Type 1 configuration read All other values are reserved	Transaction type: 1100: Normal message 1101: Vendor-defined message All other values are reserved
6:4	PCIe attributes associated with the request. 4: No Snoop 5: Relaxed Ordering 6: IDO	Same as Memory or I/O TLP	Same as Memory or I/O TLP
7	ATS bit 0	Reserved	Reserved
15:8	8: ATS bit 1 15:9: Reserved	Reserved	For vendor defined messages, this field carries bits [71:64] of the message header. For all other requests, this field is reserved.
16	If bits [8:7] are set to 2'b01 (i.e., ATS translation request) and if it is a memory read request, bit [16] is used as a no write (NW) flag. In this case the address must be aligned; that is, address bits [11:0] must be reserved as per the PCIe protocol specification.	Reserved	Reserved
19:17	PCIe Traffic Class (TC) associated with the request.	PCIe Traffic Class (TC) associated with the request.	PCIe Traffic Class (TC) associated with the request.
20	When the request is a memory write transaction, setting this bit causes the PCIe Controller to poison the memory write TLP being sent. This bit has no effect for other transaction types.	Reserved.	Reserved
21	Force ECRC insertion. Setting this bit to 1 forces the PCIe Controller to append a TLP digest containing an ECRC to the TLP, even when ECRC is not enabled for the function generating the request.	Same as Memory or I/O TLP	Same as Memory or I/O TLP
22	Enables the client to provide the bus and device numbers to be used in the requester ID. 0: The PCIe Controller uses the captured values of the bus and device numbers to form the Requester ID. 1: The PCIe Controller uses the bus and device numbers supplied by the client on bits [38:31] and [30:26] to form the requester ID. This bit must always be set while originating requests in root port mode, and the corresponding bus and device numbers must be placed on bits [38:31].	Same as Memory or I/O TLP	Same as Memory or I/O TLP
30:23	PCI function number associated with the request. ARI mode: All 8 bits are used to indicate the requesting function. Legacy mode: Only bits [25:23] are used, and bits [30:26] are used to specify the device number to be used within the requester ID, when bit [22] is set.	Same as Memory or I/O TLP	Same as Memory or I/O TLP
38:31	When bit [22] is set, this field must specify the bus number to be used for the requester ID. Otherwise, this field is ignored.	Same as Memory or I/O TLP	Same as Memory or I/O TLP
46:39	Reserved	Reserved	MSG CODE, 0x7E or 0x7F for vendor-defined messages.
49:47	Reserved	Reserved	MSG routing
57:50	TPH ST TAG [7:0]	TPH ST TAG [7:0]	TPH ST TAG [7:0]
58	TPH INDEX	TPH INDEX	TPH INDEX.
60:59	TPH TYPE [1:0]	TPH TYPE [1:0]	TPH TYPE [1:0]
61	TPH length	TPH length	TPH length
62	TPH present	TPH present	TPH present
63	PASID present	1'b0	1'b0
83:64	PASID value	20'd0	20'd0
84	Privilege mode requested	1'b0	1'b0
85	Execute mode requested	1'b0	1'b0
86	Reserved	Reserved	Zero data message
87	MASTER_AXI_AWUSER Only Valid bit to validate sideband access. 1: Descriptor is taken from [87:0] 0: Descriptor is taken from the region registers.	Same as Memory or I/O TLP	Same as Memory or I/O TLP
87	MASTER_AXI_ARUSER Only Valid bit to enable sideband access.	Valid bit to enable sideband access.	Valid bit to enable sideband access.