• Introduction
  • Features
  • Functional Description
    • Physical Layer
      • Link Initialization and Training
      • SRIS Operation
      • RX Lane Margining
        • Command Processing (Endpoint)
        • Command Processing (Root Port)
        • Step Margin Command Execution
        • Step Margin Execution Status
        • Control SKIP for Lane Margining at Receiver
        • Exception Handling
          • Command Valid Check
          • Command Supported Check
          • RX Margining PIPE Interface: Write Ack Timeout
          • Link Transition from Gen4 L0 State
    • Data Link Layer
      • Data Link Feature Exchange
        • RX Scaled Flow Control
        • TX Scaled Flow Control
        • TX Flow Control Error Handling
      • Aggregating ACK DLLPs
    • Transaction Layer
    • AXI Application Layer
      • AXI Master Read Operation
        • TLP (2 bytes, Aligned Address)
        • TLP (2n and 2n>1, up to 32 Bytes, Unaligned Address)
        • TLP (Other, up to 32 Bytes)
        • TLP Read of Lengths > 32 Bytes
        • Error Handling
        • AXI ID Handling
        • Zero Length Reads
        • Non-Contiguous Reads
      • AXI Master Write Operation
        • Poison Bit Forwarding to AXI
        • Error Handling
        • AXI ID Management
        • Zero-Length Writes
        • Non-Contiguous Writes
        • Ordering Between Posted and Non-Posted Writes
      • End-to-End Data Protection
      • Inbound Message Interface
        • Message Interface Signals
        • Message Interface FIFO Buffer
        • Message Interface Codes
      • Ordering Between AXI Master Write and Read Channels
      • Inbound PCIe to AXI Address Translation (Root Port)
      • Inbound PCIe to AXI Address Translation (Endpoint)
      • AXI Slave Interface
        • Unsupported Request Handling During Enumeration (Rootport)
        • AXI Slave Ordering
        • Completion Error Handling
        • AXI Slave Read Operation
          • Tag Management for Non-Posted Transactions
          • Error Handling
          • AXI ID Management
          • Completion Data Ordering
          • Error and Decode Errors
        • AXI Slave Write Operation
          • Error Handling
          • AXI ID Management
          • Zero-length Writes
          • Write Transaction Ordering
        • AXI Configuration and Status Registers
        • PCIe Controller Outbound Accesses
          • Outbound Access Using Regions
          • Outbound AXI-to-PCIe Address Translation Registers
          • Outbound PCIe Descriptor Registers
          • AXI Region Base Address Registers
          • Outbound Access through the Sideband Descriptor
            • MSI Memory Writes
            • MSI-X Memory Writes
          • Outstanding Non-Posted Requests
          • Ordering between AXI Slave Write and Read Channels
            • Outbound Ordering (Endpoint)
            • Outbound Ordering (Root Port)
          • Completion Error Codes
          • Completion Status Codes
        • AXI Master and Slave Read/Write Length Limitations
      • Interrupt Interface
        • Legacy Interrupt Operation
        • MSI and MSI-X Interrupt Modes
        • Interrupt Sideband Signals
    • Clock Sources
    • Link Control
      • Link Up
      • Link Down and Reset
      • Reset Types
        • Cold Reset
        • Warm Reset
        • Hot Reset
      • Reset Handshake
      • Function-Level Reset (FLR)
        • Concurrent FLR Request in Multiple PFs/VFs
        • Reset During an FLR
    • Power Management
      • Function Power States
      • L0s Power State
      • L1 Power State
        • Entering L1 via ASPM
        • Entering L1 via PCI-PM
        • L1 Exit Triggers
        • L1 Register Programming
        • Blocking L1 Explicit Client Exit or Endpoint Entry
      • L1 Power Substates
        • Entering L1 Substate
        • Exiting L1 Substate
        • L1.1 Operation
        • L1.2 Operation
        • L1 Substate Register Programming
          • Delayed Entry
          • Wait for Outstanding Completions before Entry
          • Wait for Empty Receive Buffers before Entry
          • Prevent Exit During Register Access
        • Explicit Client Exit or Entry Block
        • Integration Details
      • L2 Power State
        • Entering L2
        • Wake Up or Exiting L2
    • Configuring Registers with the APB Interface
    • Configuration Snoop Interface
    • Vendor-Specific Extended Capability (VSEC)
    • Configuration Guide
      • AXI Outbound Access Example
      • Accessing the Configuration TLP
        • Method 1
        • Method 2
      • Programming the Outbound PCIe Descriptor Register
      • Address Translation
      • Memory or I/O TLP Access
      • Message TLP Access
      • Endpoint Autonomous Link Bandwidth Management
      • Programming the SR-IOV Registers
        • VF Function Number Allocation
        • Setting up the VF BAR Registers
    • Managing Outbound NP Outstanding Requests and Completion Responses (Endpoint)
    • Interface Signals
      • Clock Signals
      • Reset Interface Signals
      • AXI Master Interface Signals
      • AXI Slave Interface Signals
      • Interrupt Interface Signals
      • Message Interface Signals
      • Status and Error Indicator Signals
      • Function-Level Reset Signals
      • Configuration Snoop Interface Signals
      • Vendor Specific (VSEC) Interface Signals
      • Power Management Interface Signals
      • L1 Interface Signals
      • L1 Substate Interface Signals
      • Hot Plug Interface Signals
      • APB Interface Signals
    • Appendix A: Acronyms and Abbreviations
    • Appendix B: Error Handling
      • Non-Fatal Errors
      • Multiple Errors
      • Multiple-Error Scenarios
    • Appendix C: LTSSM State Encoding
    • Appendix D: PCIe Configuration Capabilities Linked List
      • Configuration-Specific Capabilities
    • Appendix E: Supported Chipsets
    • Appendix E: Skew
    • Appendix F: Hot Plug Support
      • Slot Status Register Implementation
      • Slot Control Register Implementation
      • Software Notification of Hot-Plug Events
      • Register Description
        • Slot Capabilities Register
        • Slot Control Register
        • Slot Status Register
    • Revision History

    Exception Handling

    When host software writes a command into the PCIe Controller's Lane Margin Control Register, the PCIe Controller performs a Command Valid Check and a Command Supported Check.

    • Command Valid Check
    • Command Supported Check
    • RX Margining PIPE Interface: Write Ack Timeout
    • Link Transition from Gen4 L0 State
    Parent topic: RX Lane Margining