APB Interface Signals

Table 1. APB interface
Signal	Direction	Width	Clock Domain	Description
USER_APB_PADDR	Input	24	USER_APB_CLK	APB address bus. The address is the byte address of the PCIe configuration space or local management space registers.
USER_APB_PSEL	Input	1	USER_APB_CLK	Select. It indicates that the slave device is selected and that a data transfer is required. Each slave has a PSELx signal.
USER_APB_PENABLE	Input	1	USER_APB_CLK	Enable. This signal indicates the second and subsequent cycles of an APB transfer.
USER_APB_PWRITE	Input	1	USER_APB_CLK	Read or writee access. High: APB write access. Low: APB read access.
USER_APB_PWDATA	Input	32	USER_APB_CLK	Write data. Only used when USER_APB_PWRITE is high.
USER_APB_PWDATA_PAR	Input	4	USER_APB_CLK	Contains the end-to-end parity for USER_APB_PWDATA.
USER_APB_PSTRB	Input	4	USER_APB_CLK	Write the strobe signal to enable sparse data transfer on the write data bus.
USER_APB_PSTRB_PAR	Input	1	USER_APB_CLK	Contains the end-to-end parity for USER_APB_PSTRB.
USER_APB_PRDATA	Output	32	USER_APB_CLK	Read data. Only applies when USER_APB_PWRITE is low.
USER_APB_PRDATA_PAR	Output	4	USER_APB_CLK	Contains the end-to-end parity for USER_APB_PRDATA. Odd parity is computed for every byte of the data and propagated through the PCIe Controller for end-to-end parity protection.
USER_APB_PREADY	Output	1	USER_APB_CLK	Ready. The slave uses this signal to extend an APB transfer.