MSI and MSI-X Interrupt Modes

As a root port, the PCIe Controller receives MSI or MSI-X messages from downstream endpoints. It processes the messages like a normal memory write request received from the link. The PCIe Controller transfers the address and data associated with the (message) memory write request over the same target memory write interface used to transfer normal memory write requests. Software running in the root port is responsible for monitoring the writes to the MSI-assigned area in memory and servicing the interrupts.

MSI Interrupts

In this mode, the interrupt conditions are communicated from the endpoint to the root port via messages. When an interrupt condition occurs, the endpoint sends a message with information that identifies the interrupt's origin. Each message has an address and a data value to be written. Each PCI function supported by a device can be assigned a separate memory address, thus providing separate virtual channels for each function that generates interrupts. Additionally, MSI allows (and the PCIe Controller supports) a maximum of 32 distinct data patterns in the messages generated by each PCI function, and each pattern can be assigned to an interrupt condition within the function.

On the endpoint side, the client signals an interrupt condition via the AXI slave interface. The client constructs an AXI write transaction with the configured address and data value in the MSI capability structure. The client should assign the address to a region register that translates the AXI write transaction into a PCIe memory write TLP. The PCIe Controller then forwards the memory write TLP to the link. The PCIe Controller also supports 32 mask bits and pending interrupt bits for each function. When an interrupt condition occurs, the client should check that the corresponding mask bit is not set before sending the AXI write transaction. The client should read the MSI address data values from the MSI capability structure after the enumeration to construct MSI write TLPs to be sent on the AXI slave interface.

On the root port side, the PCIe Controller decodes MSI messages received from the link and passes them to the client through the AXI master interface as normal write requests.

MSI-X Interrupts

This mode is similar to MSI, except MSI-X allows a much larger number of distinct interrupt conditions to be communicated—as many as 2,048 per function—and lets you define a distinct address for each conditions. MSI-X requires the endpoint's memory to store two tables:
  • The MSI-X table contains the address and data patterns to be used for each interrupt condition as well as individual enable/mask bits.
  • The pending bit array (PBA) table stores the status of each interrupt condition.

Interrupt conditions are communicated from the endpoint to the root port via messages (write requests) like MSI mode. The PCIe Controller supports MSI-X interrupts by providing a dedicated interface to the client on the endpoint side to send MSI-X messages. The MSI-X table and PBA must be stored in client memory. When an MSI-X message is to be sent, the client communicates the message's address and data information to the PCIe Controller via an AXI slave write transaction. The client should assign the address to a region register that translates the AXI write transaction into a PCIe memory write TLP. The PCIe Controller then forwards the memory write TLP to the link.

On the root port side, the operation is similar to MSI mode. The PCIe Controller decodes MSI-X messages received from the link and passes them to the client through the AXI master interface as normal write requests.