Command Valid Check

The PCIe Controller checks for errors in the Margining Lane Control Register. Commands that do not match any defined formats are treated as invalid. If the host software writes an invalid command to the register, the PCIe Controller detects and reports the error in the Local Management Register Margining Error Status 1 Register.

The PCIe Controller logs the first error and sets the error status bit. The software must clear this status bit needs before another error can be logged. PCIe Controller continues to accept subsequent commands written by software in the Margining Lane Control Register regardless of previous errors.

Table 1. Valid Commands for EndPoint ModeAny other commands are considered invalid.

Margin Command	Margin Type[2:0]	Receiver Number[2:0]	Margin Payload[7:0]
No Command	111	000	9Ch
Report	001	110	88h to 90h
SetErrorCountLimit	010	110	{11xx_xxxx}
GoToNormalSettings	010	000, 110	0Fh
ClearErrorLog	010	000, 110	55h
StepMarginTimingOffset	011	110	{xxxx_xxxx}
StepMarginVoltageOffset	100	110	{xxxx_xxxx}
VendorDefined	101	110	{xxxx_xxxx}

Table 2. Valid Commands for Root Port ModeAny other commands are considered invalid.

Margin Command	Margin Type[2:0]	Receiver Number[2:0]	Margin Payload[7:0]
No Command	111	000	9Ch
Access Retimer	001	010, 100	{xxxx_xxxx}
Report	001	001 through 101	88h to 90h
SetErrorCountLimit	010	001 through 101	{11xx_xxxx}
GoToNormalSettings	010	000 through 101	0Fh
ClearErrorLog	010	000 through 101	55h
StepMarginTimingOffset	011	001 through 101	{xxxx_xxxx}
StepMarginVoltageOffset	100	001 through 101	{xxxx_xxxx}
VendorDefined	101	001 through 101	{xxxx_xxxx}