Clock Sources

The main PCIe Controller clock is derived directly from the PMA PLL; the clock frequency is configuration dependent. For example, the PCIe Gen4 configuration requires the PCIe Controller to run at 500 MHz.

The PCIe Controller clock domain is transparent to the user application.

Table 1. Clock Sources

Clock	Direction	Frequency (MHz)	Descriptions
AXI_CLK	Input	125 - 250	AXI interface clock.
USER_APB_CLK	Input	20 - 200	APB interface clock.
PM_CLK	Output	40	Free-running clock used for low power state transitions.

The AXI_CLK clock can be derived from a PLL output. However, you need to ensure that the AXI_CLK frequency complies with the PCIe link total bandwidth. For example, four lanes of Gen4 run at a 64 Gbps link bandwidth. To fully utilize the link bandwidth, AXI_CLK must operate at 250 MHz in your application.

The USER_APB_CLK clock can also be derived from a PLL output.

The PM_CLK is used for power management. The PCIe Controller outputs PM_CLK so you can utilize the same clock resource.

All clocks are asynchronous; the PCIe Controller handles the clock synchronization internally.

In the Efinity Interface Designer the PCIe block has an option Reference clock from on-board crystal. Efinix recommends that you turn this option off when using a reference clock slot from a PCIe slot to ensure that stable reference clock is present during PHY configuration. When this option is disabled, you need to create a PLL instance with a specific PLL resource and settings as the temporary PCIe reference clock while the PHY is configuring. When the PHY completes configuration, the reference clock reverts to the edge card connector.

If you turn this option off, use these settings:

You can use the CLKOUT4 signal as a clock source for core logic after the PHY completes configuration.