L1 Substate Register Programming

The following table provides guidance to program specification-defined registers. Refer to the Titanium PCIe® Controller Registers User Guide for the full list of registers. Registers with prefix Port and capability registers are read-only when accessed from the PCIe link. These registers are writable through the local management interface. You need to initialize these registers to match PHY and system electrical characteristics. These registers are used by the standard system initialization software to program RW control registers in the endpoint and root port L1 substate capability space.

Table 1. Root Port Inbound PCIe to AXI Address Translation Registers for 1 BAR
Register Name Guide to Select the Value Who Updates Issues with Wrong Values
Port T_POWER_ON Value and Scale Port's PHY T_POWER_ON value. For example, TP1.2_to_P1 value in the PHY. Client's controller and PHY initialization firmware PCIe system initialization software uses this value to program the T_power_on register.
T_POWER_ON Value and Scale Maximum of (endpoint Port_T_power_on, root port Port_T_power_on). Host's PCIe system initialization software If the value is lower than required, one device drives into an unpowered remote device, which can result in a link down event. The LTSSM moves to detect the state.
Port Common Mode ​Restore Time Time required for the port's PHY to establish common mode actively during the transmission of TS1s. For example, in the PHY this value is t_common_mode. Local client's controller and PHY initialization firmware. Initialization software uses this value to program the Common Mode Restore Time register.
Common Mode ​restore Time Maximum of (root port port common mode ​restore time, endpoint port common mode ​restore time). PCIe system initialization software If the value is lower than required, one device drives into an unpowered remote device, which can result in a link down event. The LTSSM moves to detect the state.
LTR_L1_2​_threshold Value and Scale
This register is used if LTR and ASPM L1.2 are enabled. It is the worst-case latency a request would face to get completed in the presence of L1.2. Refer the LTR section of the PCIe specification for the LTR usage.
An example calculation is:
LTR_L1_2_threshold = <service request latency>
+ 2 * (TL1.2 + TL1O_REFCLK_ON
+ TP1_to_P0 + TCOMMONMODE + 2 μs)
Where:
<service request latency> is the worst case delay for the root port to respond to a read request or to accept a WR request;
TL1.2 is the minimum time to stay in L1.2 (4 μs)
TL1O_REFCLK_ON is the CLKREQ# assertion to reference clock valid when exiting L1.2. This is TPOWER_ON + any additional time the system needs to enable the reference clock.
TP1_to_P0 is the time the PHY needs to change the power state from P1 to P0.
TCOMMONMODE is the same as the Port Common Mode ​Restore Time Register.
The accountable margin for latency in the PCIe Controllerand handshake is 2 μs.
The equation multiplies by two to account for the L1.2 exit that a request and/or completion might require.
 PCIe system initialization software ASPM L1.2 entry happens only when the endpoint's LTR requirement is larger than this threshold. Incorrect programming of the threshold can cause unexpected latency for the endpoint requests.